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Sun, 4 Oct 2026 05:07:47 -0700 Received: from inno-dell.home (10.127.8.11) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Sun, 4 Oct 2026 05:07:40 -0700 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Peter Colberg , Zhi Wang Subject: [PATCH v4 1/9] rust: pci: add internal SR-IOV enable and disable helpers Date: Sun, 4 Oct 2026 15:07:22 +0300 Message-ID: <20261004120732.1045629-2-zhiw@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261004120732.1045629-1-zhiw@nvidia.com> References: <20261004120732.1045629-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A7:EE_|SA1PR12MB999229:EE_ X-MS-Office365-Filtering-Correlation-Id: 162209f1-b230-43f2-3805-08df221025ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|1800799024|376014|7416014|82310400026|22082099003|18002099003|6133799003|10067099003|56012099006|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9C2l6m8qfSmQmS0pR/BA1fiIii4NeROdmR0Fqb4qFRRP8hvynZ0Uem+L3NXP/No6kZePEHVzJpYpW7Apaq2uuIyXtgwSvS+qIw9CCfYvY5zvDWo3J6oR8C1sJZPvT/em4JMpd5uhbHjd4s6Uu53ToMEm3d3y+N6htWRYoFGDB7KxnJB6ZKdoN3ZsVWM5q6j5VFOL6zW2YIMinUb/LvYFLO6mLaWNAryGc46qBZkqTUZW8fM66tdmfFgp31agvVe6a/05OMh9vuOs0GMSPTw29+o2yaQwDOspj3GfTIIz+sZD1Qv/y/PoNEs+68LAYSGqp9XMVrFuFNTyIhdh04j7KWRLv0c5PW2p4DxXgcTi5oCyUkuRWAccj4JZi2vG29Uln+wWA/Qp0Bqjw6ckVFQDEj9LOx/gNnYmZMZidhMDZBUgBqEtWy866uNbATBEbDll X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2026 12:08:05.9011 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 162209f1-b230-43f2-3805-08df221025ea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB999229 From: Peter Colberg Wrap pci_enable_sriov() and pci_disable_sriov() on Device for use by the SR-IOV callback tokens and their rollback guard. Keep these operations internal so drivers can only enable or disable VFs through the callback-scoped API introduced later in this series. Suggested-by: Danilo Krummrich Signed-off-by: Peter Colberg Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 2 ++ rust/kernel/pci/iov.rs | 46 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 rust/kernel/pci/iov.rs diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 3ec897709e89..b11a1d32c5db 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -34,6 +34,8 @@ mod id; mod io; +#[cfg(CONFIG_PCI_IOV)] +mod iov; mod irq; pub use self::id::{ diff --git a/rust/kernel/pci/iov.rs b/rust/kernel/pci/iov.rs new file mode 100644 index 000000000000..1af5bdc19830 --- /dev/null +++ b/rust/kernel/pci/iov.rs @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Abstractions for PCI Single Root I/O Virtualization (SR-IOV) drivers. + +use super::Device; + +use crate::{ + bindings, + device, + error::to_result, + prelude::*, // +}; + +impl Device> { + /// Enable the Single Root I/O Virtualization (SR-IOV) capability for this device, + /// where `nr_virtfn` is number of Virtual Functions (VF) to enable. + #[expect(dead_code)] + pub(crate) fn enable_sriov(&self, nr_virtfn: u16) -> Result { + // SAFETY: + // - `self.as_raw` returns a valid pointer to a `struct pci_dev`. + // + // - `pci_enable_sriov()` checks that the enable operation is valid: + // - the device is a Physical Function (PF), + // - SR-IOV is currently disabled, and + // - `nr_virtfn` does not exceed the total number of supported VFs. + // + // - The [`CoreInternal`] device context inherits from the [`Bound`] device context, + // which guarantees that the PF device is bound to a driver. + to_result(unsafe { bindings::pci_enable_sriov(self.as_raw(), nr_virtfn.into()) }) + } + + /// Disable the Single Root I/O Virtualization (SR-IOV) capability for this device. + #[expect(dead_code)] + pub(crate) fn disable_sriov(&self) { + // SAFETY: + // - `self.as_raw` returns a valid pointer to a `struct pci_dev`. + // + // - `pci_disable_sriov()` checks that the disable operation is valid: + // - the device is a Physical Function (PF), and + // - SR-IOV is currently enabled. + // + // - The [`CoreInternal`] device context inherits from the [`Bound`] device context, + // which guarantees that the PF device is bound to a driver. + unsafe { bindings::pci_disable_sriov(self.as_raw()) }; + } +} -- 2.53.0