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Miller" , Eric Dumazet , Gal Pressman , Jakub Kicinski , open list , Moshe Shemesh , Nimrod Oren , Or Har-Toov , Paolo Abeni , Shay Drory Subject: [PATCH mlx5-next 2/2] net/mlx5: IFC, Add capability bits for virtual LAG Date: Mon, 5 Oct 2026 11:40:47 +0300 Message-ID: <20261005084047.237081-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20261005084047.237081-1-tariqt@nvidia.com> References: <20261005084047.237081-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF0001AE19:EE_|CH3PR12MB9284:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ab29306-5249-4db5-5877-08df22bc70cb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|23010399003|10067099003|56012099006|11063799006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: v/uml/Q6cxKderRBQcgyfr5oTKXVRu2x7qHQ/i0dWXERTQ9Vy5F08/3iOnd9G9P44+AmOA+6VTWUbUS0HmFURR8fecvuoBzj43VqRrQsdXeaD24rXwofp1yYn/i8vk8r78kyCgKXzfYVDt/5JcNoKFyLFN7b1V2QW8zNRqWT9B6h7dbI0PsyVhGXgeYsMWDonUyXSpHrzWLDxyiigIwkds1Ea0DNm8XeodNY8qqr9M7cvzanxfaey/gNY6OLSSdze4OoJC5xlJZaFZBOuPuADNsv6zEVV0fI9U2DfjfhGxCbqQw+lxCLO51w3RoqLhxjW6mX5dsftkhwHuBMEUCUb5isuUY66VQCR2X3gyg5uvLqKewaCeHvN1qty/lhskGhB5bfPqybXSiR3GGInZjgNH/rjYurHShx4ZQBSvIdrWmhUMsIBD73r6oKB3iq2tWJEXaw3QkJdqF5t7S81F2ff6xuwHflNvtjbK63M6QmFPgv6xkUuTajK5gvlx0diq0UqShGWaleXDHqniCN+6cBevQuoZ3sSWmIF1bFiY1WCKNaU3WRFSimUo7SLyrRRmuft9TEIECJ4o/mfyVOkiOqQ3bpdYwX6aBgZKkAUYo5O9JCtqms3OicwYddT2QpC81/Kb1LIKlziTlx0zlZpJHgQR21q07sKNf8D6DvA9c1KjWDbrnnwgF0VTduitvc7FTuXtDPmTg/0bZbLKqOzUOr1Q== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016)(23010399003)(10067099003)(56012099006)(11063799006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1XnjxO46lDpT51i13lwlbLm0EFI5nSc1qLnTrrK/LnZ5lRZ5RGm81Bo91Qa12y7tjUzBKoXFchljaxy20IvbrKNQIsSVKDJzao9NnkxzZSQtS+y75SOHfJPR1pIQNP0ESiKAV2wu/A9KjxEuQ+zKfbKsXZdx1RA13suzsjgT1ECMWjYnvbvxix5Ro52lk9vOP96a7wwRrfutDN+83mgW+mi6m7CI6sH+jWKokVjGDYBk5E/+WTQy4rAjJISkV/GXNeBZ+3UWJte8WWWTGETCbzaUJK208FSrt2OIrf+lCAoG6cVXptUJdRPhYFEjy8BNS3l2E5q6ApF0fQ1trRMdPgPTnZgCbFANkMK7yRgnyxOwfrzlQ40ARtK2B6OnBEB/D7HTyOJK1Edzsn0MQCjLXWCujAIAEXgujPRKj5j9cQIbZ2rk7JKLbwiziBntmU+0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2026 08:41:25.1072 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ab29306-5249-4db5-5877-08df22bc70cb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE19.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9284 From: Shay Drory Virtual LAG can also be built over virtual uplinks rather than physical ports. The support for this virtual LAG is indicated by multi_uplink_eswitch and port_select_eswitch caps bit. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Reviewed-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 989408764e1b..f1ee35aa884a 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -929,7 +929,7 @@ struct mlx5_ifc_flow_table_nic_cap_bits { struct mlx5_ifc_port_selection_cap_bits { u8 reserved_at_0[0x10]; u8 port_select_flow_table[0x1]; - u8 reserved_at_11[0x1]; + u8 port_select_eswitch[0x1]; u8 port_select_flow_table_bypass[0x1]; u8 reserved_at_13[0xd]; @@ -2010,7 +2010,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_3b0[0x2]; u8 qp_latency_sensitive_disable[0x1]; u8 log_max_stride_sz_sq[0x5]; - u8 reserved_at_3b8[0x3]; + u8 reserved_at_3b8[0x1]; + u8 multi_uplink_eswitch[0x1]; + u8 reserved_at_3ba[0x1]; u8 log_min_stride_sz_sq[0x5]; u8 hairpin[0x1]; -- 2.44.0