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In k3-am62p-wakeup.dtsi, add efuse node for GP_SW registers at offset 0x230. GP_SW1 at offset 0x4 will be used to determine AM62P silicon revision. Signed-off-by: Judith Mendez Reviewed-by: Moteen Shah --- This patch adds GP_SW1 efuse node for AM62PX only now that bindings [0] are in place. Changes since v2: - Add Moteen's review tag - Fix commit description as per Moteens review [1] [0] https://lore.kernel.org/all/178942274041.683176.599438200260103620.b4-ty@kernel.org/ [1] https://lore.kernel.org/linux-devicetree/b82dec19-02a9-4b93-a2bb-3cbb6f33ae63@ti.com/ Link to v2: https://lore.kernel.org/all/20260922165714.425576-1-jm@ti.com/ --- arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 25 +++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p.dtsi | 1 + 2 files changed, 26 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi new file mode 100644 index 0000000000000..c56fb3890c983 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the AM62P WAKEUP domain peripherals + * + * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&wkup_conf { + gpsw_efuse: efuse@230 { + compatible = "ti,am62p-efuse", "socionext,uniphier-efuse"; + reg = <0x230 0x10>; + #address-cells = <1>; + bootph-all; + #size-cells = <1>; + + gpsw1: gpsw1@4 { + reg = <0x4 0x4>; + }; + }; +}; + +&chipid { + nvmem-cells = <&gpsw1>; + nvmem-cell-names = "gpsw1"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi index 9d6266d6ddb82..058f264ee0646 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -154,3 +154,4 @@ cbass_wakeup: bus@b00000 { /* Include AM62P specific peripherals */ #include "k3-am62p-main.dtsi" +#include "k3-am62p-wakeup.dtsi" -- 2.34.1