From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80CA14A384A; Tue, 6 Oct 2026 18:17:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791310662; cv=none; b=nPbDmMn1nVGFzyKnDiUURRpvuNW5iwdyr2KFO2iqH6PtYbWaGmx1VwIA/tnSPzmTsPHzmyKy7zXwb1w2IO9d8OsLMAUp76x0DW0FmNKlYpkzGfJc/l0BtCqpHdK+wNxT3NRqDlSqO4pjZg3CotP1uxsVh3pM1A5XYuV01jwXeEs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791310662; c=relaxed/simple; bh=5na1ye1r3b3uUoFfYRITaQGrO+uc1U1TUXWL/d4xE1E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=m47VBPPF2xgx/79zH8L5XiDCkni69qCUPaSrZK2g043/onJIrA8Ri8fuc6Aki7KFSYK6QY0Iw+k1rS2y719TsnYFCy28XhktYcg0ITylzwfsEhNMMEdKGiv1Cosv1AuevXkI5xa5o38P+eQxGxKR3zb8aGcpFVEND2ExUQaIZg4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=M6c/EZQy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="M6c/EZQy" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5CEB9C4AF60; Tue, 6 Oct 2026 18:17:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1791310662; bh=5na1ye1r3b3uUoFfYRITaQGrO+uc1U1TUXWL/d4xE1E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=M6c/EZQyUqYsvmgFnt384+V+fu9SeClHI5/roJxw/gVF6uOp+edo6UfhuzZrkJDHr X99tyASamQaTOuEMgoszFv+s2XmuNKq4srhMWhHHf8k6NciUXKevn9e3vLJN+Fb9SF ctdf7G/GB/fU5IVwdaDIb8p2QoQ/m3ejd0QscFglfZhlA+9L6wrlpeyjBDUjHVpybs lyFpc7ZrxwtfaH1XLj2DrJHdX86uS9jy2FvG9OMQLifheHC7H7Q1S9Fqnf2gKm5AfL l2KQR+YN9llCxqmtf0q0XCDZXRJ3WY9xEOMweeKkixR5JGFOr7cUqANck0w5G5q+qH 5VS6NB/a6KtTA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A412CA6007; Tue, 6 Oct 2026 18:17:42 +0000 (UTC) From: Fil Dunsky via B4 Relay Date: Tue, 06 Oct 2026 21:17:46 +0300 Subject: [PATCH RFC v2 08/10] ARM: dts: cortina: Add CS7542 SoC and Securifi Almond+ board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261006-b4-cs75xx-v2-8-b7d6e1e24d44@gmail.com> References: <20261006-b4-cs75xx-v2-0-b7d6e1e24d44@gmail.com> In-Reply-To: <20261006-b4-cs75xx-v2-0-b7d6e1e24d44@gmail.com> To: Arnd Bergmann , Linus Walleij , Krzysztof Kozlowski Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Jiri Slaby , Russell King , Alexandre Belloni , Drew Fustini , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Jason Li , Fil Dunsky X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791310660; l=6414; i=filipp.dunsky@gmail.com; s=20260930; h=from:subject:message-id; bh=0nk5oyU4NHYG7MtnDxJ6oGSmodiJfjttTK40N3ocFFg=; b=KKzlHw2rUv0K47tYrASP1FXkaCwoMMD/vju7wwKdJpe6jPUAQkXNbqBYLIRFfYYJ3vUPMj+7e my+lBgY3gPKCWf6U2MlmduT3LB5btqLZfEu74LiETROto8xH8VHEOn3 X-Developer-Key: i=filipp.dunsky@gmail.com; a=ed25519; pk=JAYP8e2rJ54DHOmhNtXud8rl1igAaAXoOHxtJmVXI1g= X-Endpoint-Received: by B4 Relay for filipp.dunsky@gmail.com/20260930 with auth_id=1085 X-Original-From: Fil Dunsky Reply-To: filipp.dunsky@gmail.com From: Fil Dunsky Add a minimal description of the Cortina Systems CS7542 SoC: the two Cortex-A9 cores, SCU, GIC, global timer, private timer and watchdog, PL310 L2 cache controller and the four on-chip UARTs. The peripheral clock (APB) runs at 100, 150 or 170 MHz depending on the boot strap pins. Until there is a driver for the global control block that reads the straps, model it as a fixed clock whose rate is provided by the board. The Securifi Almond+ is a touchscreen Wi-Fi router with 512 MiB of DDR3, 512 MiB of NAND flash, a QCA8337 switch, QCA9880 and AR9580 Wi-Fi and an ASM1042 USB 3.0 controller behind the SoC PCIe root ports. For now, describe the memory, the console UART and a ramoops region, and reserve the top 64 MiB of RAM which the vendor firmware hands to the packet engine queue manager. Signed-off-by: Fil Dunsky --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/cortina/Makefile | 3 + .../dts/cortina/cs7542-securifi-almondplus.dts | 55 +++++++++ arch/arm/boot/dts/cortina/cs7542.dtsi | 127 +++++++++++++++++++++ 4 files changed, 186 insertions(+) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 28fba538d55..cf4433001dd 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -12,6 +12,7 @@ subdir-y += broadcom subdir-y += calxeda subdir-y += cirrus subdir-y += cnxt +subdir-y += cortina subdir-y += gemini subdir-y += hisilicon subdir-y += hpe diff --git a/arch/arm/boot/dts/cortina/Makefile b/arch/arm/boot/dts/cortina/Makefile new file mode 100644 index 00000000000..93be6c9aedf --- /dev/null +++ b/arch/arm/boot/dts/cortina/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_CORTINA_ACCESS) += \ + cs7542-securifi-almondplus.dtb diff --git a/arch/arm/boot/dts/cortina/cs7542-securifi-almondplus.dts b/arch/arm/boot/dts/cortina/cs7542-securifi-almondplus.dts new file mode 100644 index 00000000000..e2988c68765 --- /dev/null +++ b/arch/arm/boot/dts/cortina/cs7542-securifi-almondplus.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device Tree Source for the Securifi Almond+ router + */ + +/dts-v1/; + +#include "cs7542.dtsi" + +/ { + model = "Securifi Almond+"; + compatible = "securifi,almondplus", "cortina,cs7542"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + reserved-memory { + ranges; + #address-cells = <1>; + #size-cells = <1>; + + ramoops@1bf00000 { + compatible = "ramoops"; + reg = <0x1bf00000 0x100000>; + record-size = <0x20000>; + console-size = <0x80000>; + ecc-size = <16>; + no-map; + }; + + /* Reserved for the packet engine queue manager */ + qm-buffer@1c000000 { + reg = <0x1c000000 0x4000000>; + no-map; + }; + }; +}; + +&apb_clk { + clock-frequency = <150000000>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/cortina/cs7542.dtsi b/arch/arm/boot/dts/cortina/cs7542.dtsi new file mode 100644 index 00000000000..29b0b7da866 --- /dev/null +++ b/arch/arm/boot/dts/cortina/cs7542.dtsi @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device Tree Source for the Cortina Systems CS7542 SoC + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + /* Rate is selected by the boot strap pins, set by the board */ + apb_clk: clock-apb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "apb"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + enable-method = "cortina,cs7542-smp"; + cpu-release-addr = <0 0xf00000b8>; + next-level-cache = <&l2>; + }; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@f0070110 { + compatible = "cortina,cs7542-uart"; + reg = <0xf0070110 0x30>; + interrupts = ; + clocks = <&apb_clk>; + + status = "disabled"; + }; + + uart1: serial@f0070140 { + compatible = "cortina,cs7542-uart"; + reg = <0xf0070140 0x30>; + interrupts = ; + clocks = <&apb_clk>; + + status = "disabled"; + }; + + uart2: serial@f0070170 { + compatible = "cortina,cs7542-uart"; + reg = <0xf0070170 0x30>; + interrupts = ; + clocks = <&apb_clk>; + + status = "disabled"; + }; + + uart3: serial@f00701a0 { + compatible = "cortina,cs7542-uart"; + reg = <0xf00701a0 0x30>; + interrupts = ; + clocks = <&apb_clk>; + + status = "disabled"; + }; + + l2: cache-controller@f5010000 { + compatible = "arm,pl310-cache"; + reg = <0xf5010000 0x1000>; + cache-unified; + cache-level = <2>; + arm,shared-override; + arm,tag-latency = <1 1 1>; + arm,data-latency = <1 1 2>; + }; + + scu@f8000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xf8000000 0x100>; + }; + + timer@f8000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf8000200 0x20>; + interrupts = ; + clocks = <&apb_clk>; + }; + + timer@f8000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf8000600 0x20>; + interrupts = ; + clocks = <&apb_clk>; + }; + + watchdog@f8000620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xf8000620 0x20>; + interrupts = ; + clocks = <&apb_clk>; + }; + + gic: interrupt-controller@f8001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xf8001000 0x1000>, + <0xf8000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + }; +}; -- 2.53.0