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charset="utf-8" Lane Margining at the Receiver lets software move the sampling point of a receiver in time or in voltage while the link stays up, and read back the errors the receiver sees, to find out how much margin a link running at 16.0 GT/s or faster has. pcilmr in pciutils does this today by writing the capability registers directly from user space. This series adds a debugfs interface for it. The kernel sets the link up for margining and puts it back afterwards: - ASPM is turned off for the session with the existing ASPM API, Hardware Autonomous Width/Speed Disable are set on both ends, and both ends are kept runtime resumed. All of this is undone when the session ends or either end of the link is removed. - Before each margining command, the link is checked against the state the session started in. - User space selects the receiver and the steps; the kernel does not run sweeps or interpret results. Patch 1 adds the interface and its documentation, patch 2 a kselftest. The only PCI core changes are the init/exit hooks in probe.c and remove.c and their prototypes in drivers/pci/pci.h. aspm.c, pci.c and include/linux/pci.h are not changed. Signed-off-by: Priyank Rathod --- Changes in v5: - Clarify in pcie_lmr.sh that the sysfs 'link/' directory is on the child device (PCIe Upstream Port, receiver 6) via pcie_aspm_get_link(), and rename 'up' to 'child'. - Link to v4: https://lore.kernel.org/r/20261006-pcie-link-endpoints-v4-0-ad5398c4260c@google.com Changes in v4: - Drop the exported pcie_get_link_endpoints(); the partner lookup is private to margin.c (Ilpo). - Drop pci_aspm_inhibit() and all aspm.c changes. Use pcie_aspm_enabled(), pci_disable_link_state() and pci_force_enable_link_state(), call neither when no ASPM state is enabled, and restore Clock PM when CLKREQ# was enabled. ASPM Control is checked on both ends before each command. The remaining differences after a session are documented. - Remove the MSampleMultipleReceivers capability bit. - One receiver per session, selected with a port-level 'receiver' file. A session starts with receiver 1 on a Downstream Port and 6 below it, as pcilmr does; receiver 0 is not used for margining. - Add a per-lane 'status' file with the step response and error count, and a 'port' file with the Margining Port bits. Stop writing Margining Port Status. - Locking: take both device locks with pci_dev_trylock() only while a session starts or stops, require both ends to be added, and make no runtime PM calls under the LMR locks. - End sessions from pci_lmr_exit() for either end of the link. - Commands fail with -EIO after a system suspend. - Move debugfs to pcie_lmr_ at the debugfs root. - Keep per-device state in margin.c instead of struct pci_dev. - Split the selftest into its own patch, rename it pcie_lmr, use KTAP, and only start a session on the port named by PCIE_LMR_DEV. - Refer to registers by name instead of specification section numbers. - Link to v3: https://lore.kernel.org/r/20260904-pcie-link-endpoints-v3-0-4b9a91bd4b35@google.com Changes in v3: - Link to v2: https://lore.kernel.org/r/20260904-pcie-link-endpoints-v2-0-16fcb301a3e4@google.com Changes in v2: - Link to v1: https://lore.kernel.org/r/20260831-pcie-link-endpoints-v1-1-32c2fd893e9e@google.com --- Priyank Rathod (2): PCI/LMR: Add Lane Margining at the Receiver debugfs interface selftests/pcie_lmr: Add tests for the Lane Margining debugfs interface Documentation/PCI/index.rst | 1 + Documentation/PCI/pcie-lmr.rst | 162 +++ MAINTAINERS | 8 + drivers/pci/pci.h | 8 + drivers/pci/pcie/Kconfig | 11 + drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/margin.c | 1590 ++++++++++++++++++++++++++ drivers/pci/probe.c | 1 + drivers/pci/remove.c | 1 + include/uapi/linux/pci_regs.h | 18 + tools/testing/selftests/Makefile | 1 + tools/testing/selftests/pcie_lmr/Makefile | 3 + tools/testing/selftests/pcie_lmr/pcie_lmr.sh | 311 +++++ 13 files changed, 2116 insertions(+) --- base-commit: 1ee0e2a03ac539c90fd9b8a644ae983a2216b58c change-id: 20260831-pcie-link-endpoints-978e100d5d06 Best regards, -- Priyank Rathod