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From: Gleb Pesin via B4 Relay <devnull+dormancygrace.gmail.com@kernel.org>
To: Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	 Andy Chiu <tchiu@tenstorrent.com>,
	 Charlie Jenkins <thecharlesjenkins@gmail.com>,
	stable@vger.kernel.org,  Gleb Pesin <dormancygrace@gmail.com>
Subject: [PATCH 1/3] riscv: vector: Check the xtheadvector status field in riscv_v_is_on()
Date: Tue, 06 Oct 2026 03:35:54 +0300	[thread overview]
Message-ID: <20261006-riscv-xtheadvector-vs-v1-1-b00e5abc9f7a@gmail.com> (raw)
In-Reply-To: <20261006-riscv-xtheadvector-vs-v1-0-b00e5abc9f7a@gmail.com>

From: Gleb Pesin <dormancygrace@gmail.com>

riscv_v_is_on() tests only the standard sstatus.VS field. Since commit
d863910eabaf ("riscv: vector: Support xtheadvector save/restore"),
riscv_v_enable() and riscv_v_disable() set and clear SR_VS_THEAD instead
on cores with xtheadvector, so riscv_v_is_on() returns false there even
while the vector unit is enabled.

__switch_to_vector() relies on riscv_v_is_on() to recognise a task that
is switched out inside a preemptible kernel-mode vector section. On
xtheadvector cores that check never succeeds: the outgoing task neither
disables the vector unit nor sets RISCV_PREEMPT_V_IN_SCHEDULE, and
riscv_v_enable() is skipped when the task is switched back in.

Test the status field that the running core actually uses.

Fixes: d863910eabaf ("riscv: vector: Support xtheadvector save/restore")
Cc: stable@vger.kernel.org
Assisted-by: LLM
Signed-off-by: Gleb Pesin <dormancygrace@gmail.com>
---
 arch/riscv/include/asm/vector.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index fffe72a77..910313dd0 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -128,7 +128,9 @@ static __always_inline void riscv_v_disable(void)
 
 static __always_inline bool riscv_v_is_on(void)
 {
-	return !!(csr_read(CSR_SSTATUS) & SR_VS);
+	unsigned long mask = has_xtheadvector() ? SR_VS_THEAD : SR_VS;
+
+	return !!(csr_read(CSR_SSTATUS) & mask);
 }
 
 static __always_inline void __vstate_csr_save(struct __riscv_v_ext_state *dest)

-- 
2.53.0



  reply	other threads:[~2026-10-06  0:36 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-06  0:35 [PATCH 0/3] riscv: Fix xtheadvector vector status handling Gleb Pesin via B4 Relay
2026-10-06  0:35 ` Gleb Pesin via B4 Relay [this message]
2026-10-06  0:35 ` [PATCH 2/3] riscv: Make the vendor extension headers usable from assembly Gleb Pesin via B4 Relay
2026-10-06  0:35 ` [PATCH 3/3] riscv: Disable the xtheadvector unit on kernel entry Gleb Pesin via B4 Relay

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