From: David Zhang <yidong.zhang@amd.com>
To: <quic_jhugo@quicinc.com>, <karol.wachowski@linux.intel.com>,
<max.zhen@amd.com>, <lizhi.hou@amd.com>, <ogabbay@kernel.org>,
<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>
Cc: David Zhang <yidong.zhang@amd.com>, <sonal.santan@amd.com>,
<mario.limonciello@amd.com>
Subject: [PATCH V2 05/20] accel/amdxdna: Add NPU3 classic device support
Date: Mon, 5 Oct 2026 21:22:15 -0700 [thread overview]
Message-ID: <20261006042230.547807-6-yidong.zhang@amd.com> (raw)
In-Reply-To: <20261006042230.547807-1-yidong.zhang@amd.com>
Add NPU3 classic device operations (aie4_classic_ops) and register
definitions, as well as the PCI device ID and firmware declarations for
NPU3 classic devices. Remove device IDs 0x1B0B and 0x1B0C because those
devices will not be released.
Also guard dev_heap_mm initialization and takedown against zero-sized
device heap, as NPU3 does not configure a dedicated device memory heap.
Note: System suspend/resume support requires draining and managing
in-flight commands by leveraging the kernel-mode queue (KMQ) infra.
Full suspend and resume callbacks for all AIE4 device types are
introduced in a subsequent patch with KMQ support.
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
drivers/accel/amdxdna/aie4_pci.c | 83 +++++++++++++++++++++++++
drivers/accel/amdxdna/aie4_pci.h | 1 +
drivers/accel/amdxdna/amdxdna_pci_drv.c | 23 ++++---
drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 +
drivers/accel/amdxdna/npu3_regs.c | 14 +++++
5 files changed, 115 insertions(+), 7 deletions(-)
diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c
index 3cb81bc1b627..880619e3a4a8 100644
--- a/drivers/accel/amdxdna/aie4_pci.c
+++ b/drivers/accel/amdxdna/aie4_pci.c
@@ -359,6 +359,51 @@ static void aie4_vf_hw_stop(struct amdxdna_dev_hdl *ndev)
aie4_mailbox_fini(ndev);
}
+static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev)
+{
+ int ret;
+
+ ret = aie4_fw_start(ndev);
+ if (ret)
+ return ret;
+
+ ret = aie4_mailbox_init(ndev);
+ if (ret)
+ goto stop_fw;
+
+ ret = aie4_query(ndev);
+ if (ret)
+ goto mailbox_fini;
+
+ ret = aie4_attach_work_buffer(ndev);
+ if (ret)
+ goto mailbox_fini;
+
+ ret = aie4_partition_init(ndev);
+ if (ret)
+ goto mailbox_fini;
+
+ return 0;
+
+mailbox_fini:
+ aie4_mailbox_fini(ndev);
+stop_fw:
+ aie4_fw_stop(ndev);
+ return ret;
+}
+
+static void aie4_classic_hw_stop(struct amdxdna_dev_hdl *ndev)
+{
+ struct amdxdna_dev *xdna = ndev->aie.xdna;
+
+ drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+
+ aie4_partition_fini(ndev);
+ aie4_suspend_fw(ndev);
+ aie4_mailbox_fini(ndev);
+ aie4_fw_stop(ndev);
+}
+
static int aie4_request_firmware(struct amdxdna_dev_hdl *ndev,
const struct firmware **npufw,
const struct firmware **certfw)
@@ -621,6 +666,29 @@ static int aie4_vf_init(struct amdxdna_dev *xdna)
return aie4_vf_hw_start(xdna->dev_handle);
}
+static int aie4_classic_init(struct amdxdna_dev *xdna)
+{
+ int ret;
+
+ ret = aie4m_pcidev_init(xdna);
+ if (ret)
+ return ret;
+
+ ret = aie4_alloc_work_buffer(xdna->dev_handle);
+ if (ret)
+ return ret;
+
+ ret = aie4_classic_hw_start(xdna->dev_handle);
+ if (ret)
+ goto free_work_buf;
+
+ return 0;
+
+free_work_buf:
+ aie4_free_work_buffer(xdna->dev_handle);
+ return ret;
+}
+
static void aie4_pf_fini(struct amdxdna_dev *xdna)
{
aie4_sriov_stop(xdna->dev_handle);
@@ -633,6 +701,12 @@ static void aie4_vf_fini(struct amdxdna_dev *xdna)
aie4_vf_hw_stop(xdna->dev_handle);
}
+static void aie4_classic_fini(struct amdxdna_dev *xdna)
+{
+ aie4_classic_hw_stop(xdna->dev_handle);
+ aie4_free_work_buffer(xdna->dev_handle);
+}
+
const struct amdxdna_dev_ops aie4_pf_ops = {
.init = aie4_pf_init,
.fini = aie4_pf_fini,
@@ -647,3 +721,12 @@ const struct amdxdna_dev_ops aie4_vf_ops = {
.cmd_wait = aie4_cmd_wait,
.get_aie_info = aie4_get_info,
};
+
+const struct amdxdna_dev_ops aie4_classic_ops = {
+ .init = aie4_classic_init,
+ .fini = aie4_classic_fini,
+ .hwctx_init = aie4_hwctx_init,
+ .hwctx_fini = aie4_hwctx_fini,
+ .cmd_wait = aie4_cmd_wait,
+ .get_aie_info = aie4_get_info,
+};
diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h
index bdbb2d7cf0e7..940e67347d74 100644
--- a/drivers/accel/amdxdna/aie4_pci.h
+++ b/drivers/accel/amdxdna/aie4_pci.h
@@ -96,5 +96,6 @@ static inline int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev)
extern const struct amdxdna_dev_ops aie4_pf_ops;
extern const struct amdxdna_dev_ops aie4_vf_ops;
+extern const struct amdxdna_dev_ops aie4_classic_ops;
#endif /* _AIE4_PCI_H_ */
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c
index 3140af69e29c..f5f7831c4e80 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.c
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c
@@ -28,8 +28,14 @@ MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");
MODULE_FIRMWARE("amdnpu/1502_00/npu_7.sbin");
MODULE_FIRMWARE("amdnpu/17f0_10/npu_7.sbin");
MODULE_FIRMWARE("amdnpu/17f0_11/npu_7.sbin");
+MODULE_FIRMWARE("amdnpu/17f1_10/npu.sbin");
+MODULE_FIRMWARE("amdnpu/17f1_10/cert.sbin");
MODULE_FIRMWARE("amdnpu/17f2_10/npu.sbin");
MODULE_FIRMWARE("amdnpu/17f2_10/cert.sbin");
+MODULE_FIRMWARE("amdnpu/17f1_13/npu.sbin");
+MODULE_FIRMWARE("amdnpu/17f1_13/cert.sbin");
+MODULE_FIRMWARE("amdnpu/17f2_13/npu.sbin");
+MODULE_FIRMWARE("amdnpu/17f2_13/cert.sbin");
/*
* 0.0: Initial version
@@ -55,10 +61,9 @@ MODULE_FIRMWARE("amdnpu/17f2_10/cert.sbin");
static const struct pci_device_id pci_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1502) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f0) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f1) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f2) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f3) },
- { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1B0B) },
- { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1B0C) },
{0}
};
@@ -69,10 +74,12 @@ static const struct amdxdna_device_id amdxdna_ids[] = {
{ 0x17f0, 0x10, &dev_npu4_info },
{ 0x17f0, 0x11, &dev_npu5_info },
{ 0x17f0, 0x20, &dev_npu6_info },
+ { 0x17f1, 0x10, &dev_npu3_classic_info },
{ 0x17f2, 0x10, &dev_npu3_pf_info },
{ 0x17f3, 0x10, &dev_npu3_vf_info },
- { 0x1B0B, 0x10, &dev_npu3_pf_info },
- { 0x1B0C, 0x10, &dev_npu3_vf_info },
+ { 0x17f1, 0x13, &dev_npu3_classic_info },
+ { 0x17f2, 0x13, &dev_npu3_pf_info },
+ { 0x17f3, 0x13, &dev_npu3_vf_info },
{0}
};
@@ -140,8 +147,9 @@ static int amdxdna_drm_open(struct drm_device *ddev, struct drm_file *filp)
mmgrab(client->mm);
xa_init_flags(&client->hwctx_xa, XA_FLAGS_ALLOC);
xa_init_flags(&client->dev_heap_xa, XA_FLAGS_ALLOC);
- drm_mm_init(&client->dev_heap_mm, xdna->dev_info->dev_mem_base,
- xdna->dev_info->dev_heap_max_size);
+ if (xdna->dev_info->dev_heap_max_size)
+ drm_mm_init(&client->dev_heap_mm, xdna->dev_info->dev_mem_base,
+ xdna->dev_info->dev_heap_max_size);
mutex_init(&client->mm_lock);
mutex_lock(&xdna->client_lock);
@@ -176,7 +184,8 @@ static void amdxdna_client_cleanup(struct amdxdna_client *client)
xa_for_each(&client->dev_heap_xa, heap_id, heap)
drm_gem_object_put(to_gobj(heap));
xa_destroy(&client->dev_heap_xa);
- drm_mm_takedown(&client->dev_heap_mm);
+ if (client->xdna->dev_info->dev_heap_max_size)
+ drm_mm_takedown(&client->dev_heap_mm);
mutex_destroy(&client->mm_lock);
mmdrop(client->mm);
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
index 0002e6ef32ba..953bf783b3f7 100644
--- a/drivers/accel/amdxdna/amdxdna_pci_drv.h
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
@@ -169,6 +169,7 @@ struct amdxdna_client {
/* Add device info below */
extern const struct amdxdna_dev_info dev_npu1_info;
+extern const struct amdxdna_dev_info dev_npu3_classic_info;
extern const struct amdxdna_dev_info dev_npu3_pf_info;
extern const struct amdxdna_dev_info dev_npu3_vf_info;
extern const struct amdxdna_dev_info dev_npu4_info;
diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
index 93f749acb5d5..c82433d62901 100644
--- a/drivers/accel/amdxdna/npu3_regs.c
+++ b/drivers/accel/amdxdna/npu3_regs.c
@@ -105,3 +105,17 @@ const struct amdxdna_dev_info dev_npu3_vf_info = {
.cert_feature_tbl = npu3_cert_feature_table,
.ops = &aie4_vf_ops,
};
+
+const struct amdxdna_dev_info dev_npu3_classic_info = {
+ .mbox_bar = NPU3_MBOX_BAR,
+ .sram_bar = NPU3_MBOX_BUFFER_BAR,
+ .psp_bar = NPU3_PSP_BAR_INDEX,
+ .smu_bar = NPU3_SMU_BAR_INDEX,
+ .doorbell_bar = NPU3_DOORBELL_BAR,
+ .default_vbnv = "RyzenAI-npu3",
+ .device_type = AMDXDNA_DEV_TYPE_UMQ,
+ .dev_priv = &npu3_dev_priv,
+ .fw_feature_tbl = npu3_fw_feature_table,
+ .cert_feature_tbl = npu3_cert_feature_table,
+ .ops = &aie4_classic_ops,
+};
--
2.34.1
next prev parent reply other threads:[~2026-10-06 4:23 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-06 4:22 [PATCH V2 00/20] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
2026-10-06 4:22 ` [PATCH V2 01/20] accel/amdxdna: Rename NPU3 firmware files David Zhang
2026-10-06 4:22 ` [PATCH V2 02/20] accel/amdxdna: Remove mmap for doorbell David Zhang
2026-10-06 4:22 ` [PATCH V2 03/20] accel/amdxdna: Add CERT firmware version support David Zhang
2026-10-06 4:22 ` [PATCH V2 04/20] accel/amdxdna: Upgrade firmware version to 6.0 David Zhang
2026-10-06 4:22 ` David Zhang [this message]
2026-10-06 4:22 ` [PATCH V2 06/20] accel/amdxdna: Add AIE version query to aie4_get_info David Zhang
2026-10-06 4:22 ` [PATCH V2 07/20] accel/amdxdna: Add get and set power_mode for AIE4 David Zhang
2026-10-06 4:22 ` [PATCH V2 08/20] accel/amdxdna: Add clock, DPM frequency, and resource info queries " David Zhang
2026-10-06 4:22 ` [PATCH V2 09/20] accel/amdxdna: Add context switch hysteresis with debugfs control David Zhang
2026-10-06 4:22 ` [PATCH V2 10/20] accel/amdxdna: Refactor AIE4 hardware initialization sequence David Zhang
2026-10-06 4:22 ` [PATCH V2 11/20] accel/amdxdna: Decouple AIE4 doorbell and MSI-X notify transport hooks David Zhang
2026-10-06 4:22 ` [PATCH V2 12/20] accel/amdxdna: Implement AIE4 kernel queue lifecycle and memory layout David Zhang
2026-10-06 4:22 ` [PATCH V2 13/20] accel/amdxdna: Prepare for AIE4 command submission David Zhang
2026-10-06 4:22 ` [PATCH V2 14/20] accel/amdxdna: Implement AIE4 command packet building and submission David Zhang
2026-10-06 7:12 ` Eva Crystal
2026-10-06 4:22 ` [PATCH V2 15/20] accel/amdxdna: Make hmm_invalidate common for AIE2 and AIE4 David Zhang
2026-10-06 4:22 ` [PATCH V2 16/20] accel/amdxdna: Finalize runtime PM before acquiring dev_lock on removal David Zhang
2026-10-06 7:13 ` Eva Crystal
2026-10-06 4:22 ` [PATCH V2 17/20] accel/amdxdna: Implement AIE4 suspend and resume David Zhang
2026-10-06 4:22 ` [PATCH V2 18/20] accel/amdxdna: Link SR-IOV VFs for power management sequencing David Zhang
2026-10-06 4:22 ` [PATCH V2 19/20] accel/amdxdna: Implement runtime suspend and resume support David Zhang
2026-10-06 4:22 ` [PATCH V2 20/20] accel/amdxdna: Enable AIE4 firmware logging to DRAM David Zhang
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