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Tue, 6 Oct 2026 06:05:59 -0500 From: Suraj Gupta To: Radhey Shyam Pandey , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Michal Simek , Russell King , , , , Subject: [PATCH net-next v4 2/6] dt-bindings: net: xlnx,xxv-ethernet: Add Xilinx XXV 10G/25G Ethernet Date: Tue, 6 Oct 2026 16:35:46 +0530 Message-ID: <20261006110550.1990213-3-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261006110550.1990213-1-suraj.gupta2@amd.com> References: <20261006110550.1990213-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA0PEPF0000003F:EE_|CH1PPF84B7B0C96:EE_ X-MS-Office365-Filtering-Correlation-Id: 8a4f8574-fb51-4f58-a881-08df2399d5d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700016|23010399003|82310400026|1800799024|11063799006|56012099006|10067099003|22082099003|18002099003|13003099007|3023799007; X-Microsoft-Antispam-Message-Info: 2lrE/fXhIPJA5VS8KuaPelCF5u7lcJPpcT76u/6BE3a9ZoyYWKUetRCwDO+wFKcNscN5uS3rxdrqteRfiLmSX2a2BmdbPZ4uBsyjaCtbkYbOoU+W8UWEMJlBEqB2vy6q5zOv/UV/Z21T+BfMugjUASKIvJtT5IiQGJh4NqEzxnssywynuIMbFseOH5RPL4Rh8Sve5R1EDR1gupOTjky10GbckOQzXAb+zKPNiYxcthb4JjrTR6fXkMeIimq4ZWK+/GbjOJs1JQ5WxsKqr1R1VAlAE+JCY/ygEBF2UKQdKaWr3M3mnh9QXDRjdEkWhssmHVgeAzn6MhKGDWoSlQ+/nH3j5gj7aw81p5UjMxboIozNzd/SIRC6vZQ49vVH5kxOiSLc0NFwXKgH1vspx9Xn1t6VDDRVo+U34lLycJ9L4KUlvpIcqxo8zzNO3YTg6eOi0oBE6pCPE0Cm54cAeQmtRawcPxUo15QP8kU7oWLbc8SRxulsxup9NUg4ocmhN3orwEHIOHcrUjIcDA0Sbn8P20SZF3Wn26FjUmZhteH4Dt/Bk7Xl6AFBpCTpmFklSMICalbqeyFEpiOY52+/2KqjYj6L1KHwEzFY8/a+frUZw2HyjgWo4JrTQvhkVKrQxt2YD7AuXUWFtGZPsktJt2lxVg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700016)(23010399003)(82310400026)(1800799024)(11063799006)(56012099006)(10067099003)(22082099003)(18002099003)(13003099007)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uW01jB3t8Ebu0nLiqnbtkzkoCNYMEfanRlpFathLB0/I7i8/dp6I7EemWaxkez+6AxJSJM/Ngx3OkqMOQmDtXztlU2C3JZ78DuzZxmbygbKM/upMKFw0COvrqn1pY/NlZX1VS6azZTN66WaceQtU6kyveMU/q/PmUHBwHqQYecqlFp52vp3Lupv0ABvx6Vir1Sf36J95Lk3wbYX1MZEsULc+PxpvgEKTsozz2g1vdZglN7CY9WU+4r1rtVbD0XcxtKGuGvQLDNeFcpoUzLI9njEG4GhdbpKrwuc6mttAtfgxOUML00lNnSaCEtx1zwemMAaleRIW5fzS2PbeTy6ywC26YtpZoIgCZA75t+1Ca+yCR6vl/RNcOMFXSzaHB6pnylUKvGpB3ObBSlxic/E0ssrzO8lb6I0XPQtnHWNvurfnCL5a8juPbhXxrdpJtkcq X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2026 11:06:13.4237 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a4f8574-fb51-4f58-a881-08df2399d5d9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: IA0PEPF0000003F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF84B7B0C96 The XXV Ethernet IP integrates a 10G/25G Ethernet MAC with an in-core PCS/PMA driving a high-speed serial transceiver. Its payload is moved by an external AXI DMA (or multichannel DMA) controller referenced through the dmas/dma-names properties. Document the IP in a dedicated schema file. Add the "xlnx,xxv-ethernet-1.0" compatible with the 10gbase-r and 25gbase-r phy-modes, the rx_core/drp/s_axi clocks and the AXI DMA channel properties. Signed-off-by: Suraj Gupta Reviewed-by: Rob Herring (Arm) --- .../bindings/net/xlnx,xxv-ethernet.yaml | 110 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml diff --git a/Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml new file mode 100644 index 000000000000..cf31ab677a4b --- /dev/null +++ b/Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/xlnx,xxv-ethernet.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx XXV 10G/25G Ethernet Subsystem + +maintainers: + - Radhey Shyam Pandey + - Suraj Gupta + +description: + The Xilinx XXV Ethernet Subsystem implements a 10G/25G Ethernet MAC with an + in-core PCS/PMA driving a high-speed serial transceiver. It supports the + 10GBASE-R and 25GBASE-R line rates, with 25G operation following the 25G + Ethernet Consortium specification. Because the PCS/PMA is integrated into + the IP, the subsystem has no MDIO bus master and is not managed through an + external MDIO PHY; link state is read from the MAC's own status registers. + Any SFP module management (e.g. I2C) is handled by separate IP outside this + binding. Its payload is moved by an external AXI DMA (or multichannel DMA) + controller referenced through the "dmas" property. + +properties: + compatible: + const: xlnx,xxv-ethernet-1.0 + + reg: + maxItems: 1 + description: MAC control and status register space. + + clocks: + items: + - description: RX AXI4-Stream clock. + - description: GT DRP clock. + - description: AXI4-Lite register clock. + + clock-names: + items: + - const: rx_core + - const: drp + - const: s_axi + + phy-mode: + enum: + - 10gbase-r + - 25gbase-r + + xlnx,rxmem: + description: + Size in bytes of the Rx/Tx packet buffer memory built into the IP. It is + fixed by the hardware design and bounds the largest frame (jumbo MTU) the + device can accept. + $ref: /schemas/types.yaml#/definitions/uint32 + + dmas: + minItems: 2 + maxItems: 32 + description: TX and RX DMA channel phandles. + + dma-names: + items: + pattern: "^[tr]x_chan([0-9]|1[0-5])$" + description: + Should be "tx_chan0", "tx_chan1" ... "tx_chan15" for DMA Tx channel and + "rx_chan0", "rx_chan1" ... "rx_chan15" for DMA Rx channel. + minItems: 2 + maxItems: 32 + +required: + - compatible + - reg + - clocks + - clock-names + - phy-mode + - xlnx,rxmem + - dmas + - dma-names + +allOf: + - $ref: /schemas/net/ethernet-controller.yaml# + +unevaluatedProperties: false + +examples: + # Single AXI DMA channel pair + - | + ethernet@80000000 { + compatible = "xlnx,xxv-ethernet-1.0"; + reg = <0x80000000 0x10000>; + clock-names = "rx_core", "drp", "s_axi"; + clocks = <&rx_clk>, <&drp_clk>, <&axi_clk>; + dma-names = "tx_chan0", "rx_chan0"; + dmas = <&axi_dma 0>, <&axi_dma 1>; + phy-mode = "25gbase-r"; + xlnx,rxmem = <0x8000>; + }; + # Multichannel DMA (MCDMA) with multiple Tx/Rx channels + - | + ethernet@80010000 { + compatible = "xlnx,xxv-ethernet-1.0"; + reg = <0x80010000 0x10000>; + clock-names = "rx_core", "drp", "s_axi"; + clocks = <&rx_clk>, <&drp_clk>, <&axi_clk>; + dma-names = "tx_chan0", "tx_chan1", "rx_chan0", "rx_chan1"; + dmas = <&axi_mcdma 0>, <&axi_mcdma 1>, + <&axi_mcdma 16>, <&axi_mcdma 17>; + phy-mode = "10gbase-r"; + xlnx,rxmem = <0x8000>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 72ca3aab2106..c7fecdb50cac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -29904,6 +29904,7 @@ XILINX AXI ETHERNET DRIVER M: Radhey Shyam Pandey S: Maintained F: Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml +F: Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml F: drivers/net/ethernet/xilinx/xilinx_axienet* XILINX CAN DRIVER -- 2.25.1