[PATCH] EDAC/amd64: Consolidate Family 1Ah model setup

[Vishal Badole <Vishal.Badole@amd.com>]

Every Family 1Ah model uses the v2 UMC register layout, and the driver
must select it to decode memory errors correctly.

So far each model had to select this itself. That is easy to forget when
a new model is added, and a single missed flag quietly breaks error
decoding. The driver also had no check for unknown models, so it would
load on parts that were never tested and look supported when they are
not.

Handle the layout once for the whole family so no model can miss it, and
do not load on models that are not known to work. Also add support for
the 0x88 ... 0x8f models.

Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Vishal Badole <Vishal.Badole@amd.com>
---
 drivers/edac/amd64_edac.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 0c0d11c72925..21ce1caa7151 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3887,24 +3887,25 @@ static int per_family_init(struct amd64_pvt *pvt)
 		break;
 
 	case 0x1A:
+		pvt->flags.zn_regs_v2   = 1;
+
 		switch (pvt->model) {
 		case 0x00 ... 0x1f:
 			pvt->max_mcs            = 12;
-			pvt->flags.zn_regs_v2   = 1;
 			break;
 		case 0x40 ... 0x4f:
-			pvt->flags.zn_regs_v2   = 1;
+		case 0x88 ... 0x8f:
 			break;
 		case 0x50 ... 0x57:
 		case 0xc0 ... 0xc7:
 			pvt->max_mcs            = 16;
-			pvt->flags.zn_regs_v2   = 1;
 			break;
 		case 0x90 ... 0x9f:
 		case 0xa0 ... 0xaf:
 			pvt->max_mcs            = 8;
-			pvt->flags.zn_regs_v2   = 1;
 			break;
+		default:
+			return -ENODEV;
 		}
 		break;
 
-- 
2.34.1