On Wed, Oct 07, 2026 at 11:34:54AM +0100, Lucas Tanure wrote:
> On Wed, Oct 7, 2026 at 10:51 AM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Wed, Oct 07, 2026 at 09:26:23AM +0100, Lucas Tanure wrote:
> > > The T7 has the same ethernet glue as the G12A, but the controller
> > > reaches memory through a pipeline stage that this SoC inserts in the
> > > bus path. That stage has a gate of its own, which no other member of
> > > the family has, and nothing else in Linux claims it. It is therefore
> > > switched off as unused, and the port can then no longer finish a
> > > transfer.
> > >
> > > Describing it needs a fourth clock, and the fourth clock of the
> > > existing list drives the timing adjustment logic, which the T7 never
> > > uses. So the T7 gets a list of its own with the gate in that place,
> > > under the name the SD and eMMC controllers already use.
> > >
> > > Assisted-by: LLM
> > > Signed-off-by: Lucas Tanure <tanure@linux.com>
> >
> > Didn't I ack the previous version?
> Sorry, I didn't receive one.

Hmm, thought I had sent one.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable