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Wed, 07 Oct 2026 20:24:15 -0700 (PDT) From: Matt Turner Date: Wed, 07 Oct 2026 23:24:06 -0400 Subject: [PATCH v2 3/6] alpha: describe the PTE read and write enable bits Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261007-alpha-hugepages-v2-3-8e108af2d961@gmail.com> References: <20261007-alpha-hugepages-v2-0-8e108af2d961@gmail.com> In-Reply-To: <20261007-alpha-hugepages-v2-0-8e108af2d961@gmail.com> To: Richard Henderson , Magnus Lindholm , Axel Rasmussen , Andrew Morton , Peter Xu Cc: linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, Matt Turner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2280; i=mattst88@gmail.com; h=from:subject:message-id; bh=V0j0CtHFz14eefLCzb5WnjuHMOvELhvyZG5FMWdbC7w=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLKO81xp2W+T/zp93iuFqknnOELzavhWrbYrC9yzprL1V OtJeU2Bjo8sDGJcDDPFFFni1iuyzGrbsdTntPQvmDmsTCBDpEUaGICAhYEvNzGv1EjHSM9U21DP EMjQMYqHyOkxaGQWF5emFummFRQ55OWXJJZk5ucV6+UXpOYVpBfopWWmlWRk5BcVpwKN0MtLLTF 1dXQzMjQwsXS0MHOycDQ1cXZ2MnRyc3R0dnUysjQ3MXC2dDRxtTRn4OIUgLlG2Zvhf0SiBfsqkx nTXnOd73uqYj1vmkTkHNOKV1WHWMpOt0/J6mH4p391xmmV/l05WRERtlMPK2U4LfPc2fnpWoecd FD0xMo2LgA= X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A The comments on _PAGE_KRE and _PAGE_URE said only "xxx". Describe the four enable bits as the Alpha Linux PTE defines them, in Table 22-3 of the Alpha Architecture Reference Manual: kernel and user read enable in bits 8 and 9, kernel and user write enable in bits 12 and 13, with bits <11:10> and <15:14> reserved. There are only two processor modes, user and kernel (section 22.5.1). Linux uses the read enables as its accessed bit and the write enables as its dirty bit, so say which of __ACCESS_BITS and __DIRTY_BITS each one belongs to. The names differ from what the hardware calls those bits on the 21264. Its PALcode loads the PTE unchanged into DTB_PTE (21264/EV67 Hardware Reference Manual, section 6.9), where bits 9 and 13 are the Executive read and write enables (Figure 5-27), Executive being mode 1 of the four the processor implements (Table 5-5). That is a detail below the PALcode interface, and it is also the layout of the OpenVMS PTE in Table 11-2, which is not the one Linux uses. No functional change. Suggested-by: Magnus Lindholm Signed-off-by: Matt Turner --- arch/alpha/include/asm/pgtable.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/alpha/include/asm/pgtable.h b/arch/alpha/include/asm/pgtable.h index 8a175e0c2b42..d22e28b956fb 100644 --- a/arch/alpha/include/asm/pgtable.h +++ b/arch/alpha/include/asm/pgtable.h @@ -65,10 +65,10 @@ struct vm_area_struct; #define _PAGE_FOW 0x0004 /* used for page protection (fault on write) */ #define _PAGE_FOE 0x0008 /* used for page protection (fault on exec) */ #define _PAGE_ASM 0x0010 -#define _PAGE_KRE 0x0100 /* xxx - see below on the "accessed" bit */ -#define _PAGE_URE 0x0200 /* xxx */ -#define _PAGE_KWE 0x1000 /* used to do the dirty bit in software */ -#define _PAGE_UWE 0x2000 /* used to do the dirty bit in software */ +#define _PAGE_KRE 0x0100 /* kernel read enable, in __ACCESS_BITS */ +#define _PAGE_URE 0x0200 /* user read enable, in __ACCESS_BITS */ +#define _PAGE_KWE 0x1000 /* kernel write enable, in __DIRTY_BITS */ +#define _PAGE_UWE 0x2000 /* user write enable, in __DIRTY_BITS */ /* .. and these are ours ... */ #define _PAGE_DIRTY 0x20000 -- 2.55.0