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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1615f1ac8c5sm7374730c88.2.2026.10.06.23.50.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Oct 2026 23:51:04 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 07 Oct 2026 12:20:45 +0530 Subject: [PATCH 2/4] clk: qcom: clk-alpha-pll: Skip Zonda PLL configuration if already enabled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261007-ipq9650_apss_clk-v1-2-fd4c2b3cbdea@oss.qualcomm.com> References: <20261007-ipq9650_apss_clk-v1-0-fd4c2b3cbdea@oss.qualcomm.com> In-Reply-To: <20261007-ipq9650_apss_clk-v1-0-fd4c2b3cbdea@oss.qualcomm.com> To: Georgi Djakov , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.15.2 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDAyNyBTYWx0ZWRfX7iL15qKwrMxx HYp2V9WkzpMWlBYIvVRJRMPUgnteXFlP2eNeAerkccm78WC5PhyQLSetxFVd7Lfm15naQKAxejT LW4L0Utx5QOSh61JWhqbYVwmv53G/XM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDAyNyBTYWx0ZWRfXxMFnirVpqIMM qdIAPZMw4Q+k6y1YSqMdX5anAN4+CV4tsH6kOUk/Zt5LI1+t0mix2ywM8W7VTDXOrx8Nq+dLT6d v26Zf6o7ZF4mpHOX5oLtxzfWrzlN9j7WdxkyqtnyR5kSK2fjsKzGe+y8LRs4Km9aabkwEHYLgHk OfrWuOsdB7MHGAOJ7znSZbPtR38JKMz9EZbDsedP79B8bZQGhJ5rRHAz+JHLmd1CHhEm3kqWZEB OLWEwbFmae1Y/1VN0kvCS+WauHG+eUNNsFP5C9rHMGhmp8jZfBGJZ4n5WgmDE4fLxaiNhKfpMw1 dFWCJlLhikQ2HmgjKMpzeZbFBj4DN6mPoyRPnqusIwe2O6yUcll4NM1AzHhj3ETGFBAQCjzyoKB jyPu9NkpwB2ADOzsNV0gnHq2UO/IEO4um9y+ZViNTVcJRh68zxyTnw3PqKShUZz3pV/+OtIhcWf fh1PH6lOBiRmJtEN4Bw== X-Proofpoint-GUID: U7LRUmTZf7Lv-d_cUqmxP_lfcXNEsLNY X-Proofpoint-ORIG-GUID: U7LRUmTZf7Lv-d_cUqmxP_lfcXNEsLNY X-Authority-Analysis: v=2.4 cv=LvYHWXdc c=1 sm=1 tr=0 ts=6ac5ebd9 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=HvQ8q7LFvqEYzEKEMhkA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_02,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070027 On IPQ9650, the bootloader configures and enables the APSS Zonda PLL that provide the clocks for the A55 CPU cores and L3 interconnect. When the APSS clock driver probes, it attempts to reconfigure the already running PLLs. As part of the reconfiguration sequence, the PLL output is disabled and the PLL is placed into standby before being re-enabled. Since the CPUs are actively clocked from these PLLs, removing the clock during this window causes the system to hang. Avoid reconfiguring PLLs that are already enabled and return early, similar to clk_trion_pll_configure(). Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/clk-alpha-pll.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 60173b076cc5..3641b2da92cd 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -2162,6 +2162,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { + /* Check if PLL is already enabled */ + if (trion_pll_is_enabled(pll, regmap)) + return; + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); -- 2.34.1