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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1615f1ac8c5sm7374730c88.2.2026.10.06.23.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Oct 2026 23:51:09 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Wed, 07 Oct 2026 12:20:46 +0530 Subject: [PATCH 3/4] dt-bindings: clock: ipq9650-apss-clk: Add IPQ9650 apss clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261007-ipq9650_apss_clk-v1-3-fd4c2b3cbdea@oss.qualcomm.com> References: <20261007-ipq9650_apss_clk-v1-0-fd4c2b3cbdea@oss.qualcomm.com> In-Reply-To: <20261007-ipq9650_apss_clk-v1-0-fd4c2b3cbdea@oss.qualcomm.com> To: Georgi Djakov , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.15.2 X-Proofpoint-ORIG-GUID: etLse5Yf0iZCoxevnpO_SAwOXAXsFYl7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDAyNyBTYWx0ZWRfX19iBPURKbL+Y s+jECoX20FX2kSoNDyrGgm8GTbBbF9ITqnK9vxQh01FzuOt9tr9Z9vDvENeuNLMsLT612PGf+KP Vr30HO2uovEarUVGP/fqN9GXIkFP1vxRJF2tZFtj89uY1yma82TfZ5VxwxdE5KIWnLU5t3fgFg9 JyAz/+w3JZHPaJkaRODG25WZXw7NgfaujzN3KrhYwW62VcIXJkS8DbQNC3jfy1Toy+a0aJT+snl 2SAh9tyYrAvOVn+OsI8b7E2NLNWemV9rRW6fYcAzyRACpgpGVV9vhS1FMLSAImPHlsxWVZEvVFB zy+izycKt/8gpuMATUmOhUiQ50q4cIIRKvTvGvz/IVvxcaJ58i7d9o+ZsQolK6HFwz65UFR5XVw dstVVPnXtw9EZdNGo+REN04ZyDjkO/RvD3NodimwWVuUQL41wNl8cri6cN+8bY/JeyI6PQnIP+z 5EHxPp3ou/pyIaK+Hzg== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDAyNyBTYWx0ZWRfXwHAWlkzm2ht1 gbMu76pDPudsQntzi2dZLQLHoMZFFh/XZp5SSpSobZzjVqb6/7YBspS1cwuSWWUuIonxx2ro0UT 2OGzr2iRKeHUi9a0HlIQznijX6+oTT0= X-Proofpoint-GUID: etLse5Yf0iZCoxevnpO_SAwOXAXsFYl7 X-Authority-Analysis: v=2.4 cv=NatzRGD4 c=1 sm=1 tr=0 ts=6ac5ebe3 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=QDl9-_pjA6WZ_EjsUeIA:9 a=QEXdDO2ut3YA:10 a=vBUdepa8ALXHeOFLBtFW:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_02,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070027 The APSS clock controller on IPQ9650 provides the CPU and L3 clocks and has a register space separate from the GCC. The four Cortex-A55 cores, the Cortex-A78 core and the L3 are each clocked by their own Zonda PLL, selected through a glitch-free mux whose parents are XO, GPLL0 and the corresponding PLL. The L3 needs to be scaled along with the CPUs, so the controller is also an interconnect provider. Add the binding, the clock indices for the Cortex-A78 (gold) cluster to the shared APSS header, and the interconnect IDs for the CPU and L3 nodes. Signed-off-by: Kathiravan Thirumoorthy --- .../bindings/clock/qcom,ipq9650-apss-clk.yaml | 58 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,apss-ipq.h | 5 ++ include/dt-bindings/interconnect/qcom,ipq9650.h | 4 ++ 3 files changed, 67 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9650-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9650-apss-clk.yaml new file mode 100644 index 000000000000..6b47183edd56 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9650-apss-clk.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9650-apss-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm APSS IPQ9650 Clock Controller + +maintainers: + - Kathiravan Thirumoorthy + +description: + The APSS clock controller provides the CPU and L3 clocks on IPQ9650 and + has a register space separate from the GCC. The four Cortex-A55 cores, + the Cortex-A78 core and the L3 are each clocked by their own Zonda PLL. + Each clock is selected through a glitch-free mux (GFM) whose parents are + XO, GPLL0 and the corresponding PLL. + +properties: + compatible: + enum: + - qcom,ipq9650-apss-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference to the XO clock. + - description: Reference to the GPLL0 clock. + + '#clock-cells': + const: 1 + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + #include + + apss_clk: clock-controller@fa80000 { + compatible = "qcom,ipq9650-apss-clk"; + reg = <0x0fa80000 0x30000>; + clocks = <&xo_board>, + <&gcc GPLL0>; + #clock-cells = <1>; + #interconnect-cells = <1>; + }; diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h index 0bb41e5efdef..c9b04f2dbb6c 100644 --- a/include/dt-bindings/clock/qcom,apss-ipq.h +++ b/include/dt-bindings/clock/qcom,apss-ipq.h @@ -15,4 +15,9 @@ #define L3_CLK_SRC 6 #define L3_CORE_CLK 7 +/* IPQ9650 Gold cluster clock indices */ +#define APSS_GOLD_PLL 8 +#define APSS_GOLD_PLL_POSTDIV 9 +#define APSS_GOLD_CORE_CLK 10 + #endif diff --git a/include/dt-bindings/interconnect/qcom,ipq9650.h b/include/dt-bindings/interconnect/qcom,ipq9650.h index 023a3878cc08..1a77609de832 100644 --- a/include/dt-bindings/interconnect/qcom,ipq9650.h +++ b/include/dt-bindings/interconnect/qcom,ipq9650.h @@ -25,4 +25,8 @@ #define MASTER_SNOC_USB 20 #define SLAVE_SNOC_USB 21 +#define MASTER_CPU_SILVER 0 +#define SLAVE_L3 1 +#define MASTER_CPU_GOLD 2 + #endif /* INTERCONNECT_QCOM_IPQ9650_H */ -- 2.34.1