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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN1PEPF00018073.mail.protection.outlook.com (10.167.245.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.496.14 via Frontend Transport; Wed, 7 Oct 2026 03:52:05 +0000 Received: from BLRKPRNAYAK.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Tue, 6 Oct 2026 22:51:59 -0500 From: K Prateek Nayak To: Peter Zijlstra , Chen Yu , "Tim Chen" , Ingo Molnar , Juri Lelli , Vincent Guittot , "Andrew Morton" , Arnd Bergmann , , , , , , , , Huacai Chen CC: Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Shrikanth Hegde , K Prateek Nayak , "WANG Xuerui" Subject: [RFC PATCH v3.1 04/13] LoongArch: Configure sbm topology during SMP preparation Date: Wed, 7 Oct 2026 03:51:35 +0000 Message-ID: <20261007035135.3819-1-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261001192849.74788-5-kprateek.nayak@amd.com> References: <20261001192849.74788-5-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00018073:EE_|DS0PR12MB7850:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d264537-46a1-488c-0378-08df24265ac7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|1800799024|82310400026|376014|36860700016|921020|10067099003|11063799006|22082099003|56012099006|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: o8Yfs8RA2sGVSuVhTXM8TpUpZxt5pX7IfTK/UYInrW0/M6zOlDTuODa3jqa0B/Wu2027v/nQu7AH+NIlH7TozFi1cKiI4u8GgTuNcvL7WQfPBGf4uAfuIY3MJLpTdBC1AdEMJqxLCaNsKLihHyuHHzzvHf46NQUx53KFpPm1lNUokMVM3u3cBhrEgXHSU1Lolw6dUtptaISc2rHuOYNdyPmcxu807fjATfeGkiGmFj3ZYa8AcQeNzJ2rBIY/lrRZZxZqbMM+P5sNL1NyKzRvsrketuVrAWQdGSKNeYBqsajLe2LB95cWpjzSwD0mWclgZizEMWAKmWQGcVmA0PLCawz5zhIo36BYg+zSwUsPnJgiE7oKmqPJlzsgwEsCFx/H1Evb5ZcUuMx1B6znKhwxmpbUxA3coYqBWJHFiESv/Dk52Yf0iI9Ewtk17sEQVIkz X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2026 03:52:05.9817 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d264537-46a1-488c-0378-08df24265ac7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00018073.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7850 Configure the sparsebitmask (sbm) topology for multi-node processors once SRAT is parsed and early_cpu_to_node() mappings are stable. The _PXM mappings are not reliable for disabled CPUs, and the worst case scenario is considered where the disabled CPUs can either form their own NUMA node (increases num_instances) or joins the node with the largest CPU count (increases max_cpus_per_instance). Since the final topology cannot be predicted at boot time, both are incremented with the count of disabled CPUs to account for topology going either ways. The sbm core will limit traversals to the nodes that are onlined and it is acceptable to overshoot the final limits. Signed-off-by: K Prateek Nayak --- Changelog rfc v3 .. rfc v3.1: o Alternate scheme to use disabled CPUs to find the worst case topology instead of relying of incorrect changes to SRAT parsing. This was cross-compiled and tested on QEMU with: qemu-system-loongarch64 \ -machine virt \ -m 4G \ -cpu la464 \ -smp sockets=2,cores=8 \ -bios QEMU_EFI.fd \ -kernel arch/loongarch/boot/vmlinuz.efi \ -initrd ramdisk \ -serial stdio \ -append "root=/dev/ram rdinit=/sbin/init console=ttyS0,115200" \ -object memory-backend-ram,size=2G,id=mem0 \ -object memory-backend-ram,size=2G,id=mem1 \ -numa node,nodeid=0,memdev=mem0,cpus=0-7 \ -numa node,nodeid=1,memdev=mem1,cpus=8-15 ... The incorrect SRAT parsing changes from v3 Patch 03/13 is no longer required with this alternate fallback. --- arch/loongarch/kernel/smp.c | 52 +++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/loongarch/kernel/smp.c b/arch/loongarch/kernel/smp.c index d4b5d1b6bb01..6cf1f5ada038 100644 --- a/arch/loongarch/kernel/smp.c +++ b/arch/loongarch/kernel/smp.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -73,6 +74,10 @@ static cpumask_t cpu_llc_shared_setup_map; /* representing cpus for which core maps can be computed */ static cpumask_t cpu_core_setup_map; +/* sbm setup data - only needed during init */ +static cpumask_t cpu_sbm_setup_map __initdata; +static int __node_thread_count[NR_CPUS] __initdata; + struct secondary_data cpuboot_data; static DEFINE_PER_CPU(int, cpu_state); @@ -362,10 +367,17 @@ void __init loongson_smp_setup(void) pr_info("Detected %i available CPU(s)\n", loongson_sysconf.nr_cpus); } +int arch_sbm_cpu_instance_id(int cpu) +{ + return cpu_to_node(cpu); +} + void __init loongson_prepare_cpus(unsigned int max_cpus) { int i = 0; + int disabled_cpus = 0; int threads_per_core = 0; + int num_sbm_instances, max_threads_per_instance = 1; parse_acpi_topology(); cpu_data[0].global_id = cpu_logical_map(0); @@ -388,6 +400,46 @@ void __init loongson_prepare_cpus(unsigned int max_cpus) per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; cpu_smt_set_num_threads(threads_per_core, threads_per_core); + + for_each_possible_cpu(i) { + unsigned int node = early_cpu_to_node(i); + bool found = false; + int j; + + if (node == NUMA_NO_NODE) { + disabled_cpus++; + continue; + } + + for_each_cpu(j, &cpu_sbm_setup_map) { + if (node == early_cpu_to_node(j)) { + found = true; + break; + } + } + + if (!found) { + cpumask_set_cpu(i, &cpu_sbm_setup_map); + __node_thread_count[i] = 1; + continue; + } + + __node_thread_count[j] += 1; + max_threads_per_instance = max(max_threads_per_instance, + __node_thread_count[j]); + } + + /* + * In case of disabled CPUs, expect them to either show up as a + * new node or get added to the largest NUMA node. + * + * XXX: Is there a way to establish the correct CPU <-> node + * relation for CPUs that have disabled APIC? + */ + num_sbm_instances = cpumask_weight(&cpu_sbm_setup_map) + disabled_cpus; + max_threads_per_instance += disabled_cpus; + + sbm_set_topology(num_sbm_instances, max_threads_per_instance); } /* -- 2.34.1