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Additionally, fix the register sizes for these PLL configuration registers to 16 bits. Signed-off-by: Kate Hsuan --- drivers/media/i2c/imx471.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/media/i2c/imx471.c b/drivers/media/i2c/imx471.c index bc6bf11ecf31..b469fef7eef9 100644 --- a/drivers/media/i2c/imx471.c +++ b/drivers/media/i2c/imx471.c @@ -68,15 +68,24 @@ #define IMX471_EXT_CLK 19200000 /* PLL */ -#define IMX471_REG_VTPXCK_DIV CCI_REG8(0x0301) -#define IMX471_REG_VTSYCK_DIV CCI_REG8(0x0303) -#define IMX471_REG_PREPLLCK_VT_DIV CCI_REG8(0x0305) +#define IMX471_REG_VTPXCK_DIV CCI_REG16(0x0300) +#define IMX471_REG_VTSYCK_DIV CCI_REG16(0x0302) +#define IMX471_REG_PREPLLCK_VT_DIV CCI_REG16(0x0304) #define IMX471_REG_PLL_VT_MPY CCI_REG16(0x0306) -#define IMX471_REG_OPPXCK_DIV CCI_REG8(0x0309) -#define IMX471_REG_OPSYCK_DIV CCI_REG8(0x030b) +#define IMX471_REG_OPPXCK_DIV CCI_REG16(0x0308) +#define IMX471_REG_OPSYCK_DIV CCI_REG16(0x030a) +#define IMX471_REG_OP_PREPLLCK_DIV CCI_REG16(0x030c) +#define IMX471_REG_OP_MPY CCI_REG16(0x030e) #define IMX471_REG_PLL_MULT_DRIV CCI_REG8(0x0310) #define IMX471_PLL_SINGLE 0 #define IMX471_PLL_DUAL 1 +#define IMX471_VTPXCK_DIV 6 +#define IMX471_VTSYCK_DIV 2 +#define IMX471_PREPLLCK_VT_DIV 2 +#define IMX471_PLL_VT_MPY 121 +#define IMX471_OPSYCK_DIV 1 +#define IMX471_PLL_OP_MPY 83 +#define IMX471_PREPLLCK_OP_DIV 2 /* IMX471 native and active pixel array size */ #define IMX471_NATIVE_WIDTH 4672 @@ -236,14 +245,13 @@ static const struct cci_reg_sequence mode_1928x1088_regs[] = { { IMX471_REG_DIG_CROP_HEIGHT, 1088 }, { IMX471_REG_X_OUTPUT_SIZE, 1928 }, { IMX471_REG_Y_OUTPUT_SIZE, 1088 }, - { IMX471_REG_VTPXCK_DIV, 0x06 }, - { IMX471_REG_VTSYCK_DIV, 0x02 }, - { IMX471_REG_PREPLLCK_VT_DIV, 0x02 }, - { IMX471_REG_PLL_VT_MPY, 0x0079 }, - { IMX471_REG_OPSYCK_DIV, 0x01 }, - { CCI_REG8(0x030d), 0x02 }, - { CCI_REG8(0x030e), 0x00 }, - { CCI_REG8(0x030f), 0x53 }, + { IMX471_REG_VTPXCK_DIV, IMX471_VTPXCK_DIV }, + { IMX471_REG_VTSYCK_DIV, IMX471_VTSYCK_DIV }, + { IMX471_REG_PREPLLCK_VT_DIV, IMX471_PREPLLCK_VT_DIV }, + { IMX471_REG_PLL_VT_MPY, IMX471_PLL_VT_MPY }, + { IMX471_REG_OPSYCK_DIV, IMX471_OPSYCK_DIV }, + { IMX471_REG_OP_PREPLLCK_DIV, IMX471_PREPLLCK_OP_DIV }, + { IMX471_REG_OP_MPY, IMX471_PLL_OP_MPY }, { IMX471_REG_PLL_MULT_DRIV, IMX471_PLL_DUAL }, { CCI_REG8(0x3f4c), 0x81 }, { CCI_REG8(0x3f4d), 0x81 }, -- 2.55.0