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([179.179.237.181]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-7ca218138c6sm1319958137.12.2026.10.07.02.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Oct 2026 02:34:08 -0700 (PDT) From: Vinicius Pedrosa To: Andre Przywara , linux-serial@vger.kernel.org Cc: gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andriy.shevchenko@linux.intel.com, ilpo.jarvinen@linux.intel.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Enzo Adriano Subject: Re: [PATCH 3/3] serial: 8250_dw: Add Allwinner A733 UART Date: Wed, 7 Oct 2026 06:33:23 -0300 Message-ID: <20261007093323.22104-1-vinicius.eduardo.pedrosa@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261006193046.540252-1-vinicius.eduardo.pedrosa@gmail.com> References: <20261005172538.398522-1-vinicius.eduardo.pedrosa@gmail.com> <20261005172538.398522-4-vinicius.eduardo.pedrosa@gmail.com> <603b4f40-2a60-4bc5-8b98-ada7a52fead9@arm.com> <20261006193046.540252-1-vinicius.eduardo.pedrosa@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Andre, Correction to my last mail: the v2 change I proposed there is wrong. Gating only when clk_round_rate() differs from the current rate is e5d6bd25f93d ("serial: 8250_dw: Do not reclock if already at correct rate"). 7dfae6cbadc1 reverted it because it broke the dw UARTs on Bay Trail and Cherry Trail. Mine compares against clk_get_rate() instead of p->uartclk. Peter suggested that variant in the revert thread, and Hans pointed out it's the same check, since uartclk comes from clk_get_rate() at probe. >From my reading of clk.c, the flag you mentioned seems to explain the regression. The LPSS "-update" gate is registered with CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE in drivers/acpi/x86/lpss.c. Preparing it rate-protects the gate and its divider parent, and while they're protected clk_round_rate() returns the current rate. So the check always says there's nothing to do. The divider never gets reprogrammed. Hans's debug log in <20240317214123.34482-1-hdegoede@redhat.com> has a request for 1843200 rounded to 153600, the rate already set. I can't test LPSS. So on LPSS the CCF does ask for the gate, and the disable/enable in dw8250_set_termios() is how the driver gets clk_set_rate() past it. For v2 I'm inclined to keep SKIP_SET_RATE for the A733, like JH7100 (b0ad20a3b64b) and SG2044 (cad4dda82c7e). The A733 bus-uart gates carry no rate flags, so the rate calls there are no-ops. Calling clk_set_rate() with the clock running and gating only on -EBUSY might work for everyone, but it needs BYT/CHT testing I can't do. This is separate from DLF. v2 still uses your 2^n - 1 check for that, with no A733 quirk. Thanks, Vinicius