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From: kai zhang <zhangkai.cool@gmail.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Logan Gunthorpe <logang@deltatee.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH] PCI/P2PDMA: Add Intel 0x6f00 host bridge to the whitelist
Date: Wed,  7 Oct 2026 22:15:58 +0800	[thread overview]
Message-ID: <20261007141558.59852-1-zhangkai.cool@gmail.com> (raw)

For P2P paths routed through a host bridge, the P2PDMA core consults a
whitelist of known-good hardware. Add Intel 8086:6f00 with
REQ_SAME_HOST_BRIDGE so the entry permits peers only below the same host
bridge.

The bridge was tested on a single-socket Intel Xeon E5-2697A v4 system
with two PCIe GPUs below different Root Ports of the same host bridge.
Without the whitelist entry, peer access was rejected before a transfer
was issued. With the entry, 64 MiB peer transfers completed in both
directions with data integrity verified while the IOMMU used translated
mode.

Assisted-by: LLM
Signed-off-by: kai zhang <zhangkai.cool@gmail.com>
---
 drivers/pci/p2pdma.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
index 9334eb314663..84413920e39b 100644
--- a/drivers/pci/p2pdma.c
+++ b/drivers/pci/p2pdma.c
@@ -542,6 +542,7 @@ static const struct pci_p2pdma_whitelist_entry {
 	/* Intel Xeon E5/Core i7 */
 	{PCI_VENDOR_ID_INTEL,	0x3c00, REQ_SAME_HOST_BRIDGE},
 	{PCI_VENDOR_ID_INTEL,	0x3c01, REQ_SAME_HOST_BRIDGE},
+	{PCI_VENDOR_ID_INTEL,	0x6f00, REQ_SAME_HOST_BRIDGE},
 	/* Intel Xeon E7 v3/Xeon E5 v3/Core i7 */
 	{PCI_VENDOR_ID_INTEL,	0x2f00, REQ_SAME_HOST_BRIDGE},
 	{PCI_VENDOR_ID_INTEL,	0x2f01, REQ_SAME_HOST_BRIDGE},
-- 
2.54.0 (Apple Git-157)


             reply	other threads:[~2026-10-07 14:16 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-07 14:15 kai zhang [this message]
2026-10-07 21:59 ` Bjorn Helgaas

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