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Wed, 07 Oct 2026 15:22:37 -0700 (PDT) Received: from cachyos-aura ([45.112.148.99]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-16375a1f898sm5386947c88.0.2026.10.07.15.22.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Oct 2026 15:22:37 -0700 (PDT) From: Navon John Lukose To: Andi Shyti , Mika Westerberg , linux-i2c@vger.kernel.org Cc: Navon John Lukose , Andy Shevchenko , linux-kernel@vger.kernel.org Subject: [PATCH v2] i2c: designware: size the RX FIFO threshold to the queued transfer Date: Thu, 8 Oct 2026 03:52:31 +0530 Message-ID: <20261007191911.502428-1-navonjohnlukose@gmail.com> X-Mailer: git-send-email 2.56.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit i2c_dw_xfer_msg() leaves DW_IC_RX_TL at the 0 that i2c_dw_configure_mode() writes, so the controller raises RX_FULL once per received byte. Program RX_TL from the reads already queued, capped at half the FIFO until the last message is queued, so there is room for the rest. On an Arrow Lake-H LPSS core with rx_fifo_depth 32, a 22-byte HID input report costs 2.00 interrupts instead of 21.43, and a 452-byte descriptor 0.14 interrupts per byte instead of 1.64. Polling the touchpad with HIDIOCGINPUT at 142 Hz draws 1.58 W less platform power (psys, 32 paired runs). Acked-by: Mika Westerberg Assisted-by: LLM Signed-off-by: Navon John Lukose --- v2: - Drop the cpu_dma_latency figure, which read as advice to set it, and move the latency figure here with where it comes from (Andy) - Add the platform power figure - Add Mika's Acked-by - Rebase on i2c/i2c-host v1: https://lore.kernel.org/all/20260919232647.448748-1-navonjohnlukose@gmail.com/ Mean HIDIOCGINPUT latency rises from 2522 to 3268 us, 94% of it exit latency from the deeper idle states the CPU now reaches between interrupts. Since v1, also tested on a Goodix touchscreen on a second controller with 7, 21 and 64 byte reports; 64 exceeds rx_fifo_depth and exercises the half-FIFO cap. Still untested: a RECV_LEN continuation longer than one byte, and cores with rx_fifo_depth below 4. drivers/i2c/busses/i2c-designware-master.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c index 7a301c8..f52f52b 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -376,7 +376,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) { struct i2c_msg *msgs = dev->msgs; u32 intr_mask; - int tx_limit, rx_limit; + int tx_limit, rx_limit, rx_tl; u32 buf_len = dev->tx_buf_len; u8 *buf = dev->tx_buf; bool need_restart = false; @@ -482,6 +482,19 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) if (dev->msg_err) intr_mask = 0; + /* + * Size the RX FIFO threshold to the reads already queued, so the + * controller raises one RX_FULL for the whole burst instead of one per + * received byte. While messages remain to be queued, cap it so RX_FULL + * still arrives in time to drain the FIFO and let the next TX_EMPTY + * queue the rest. + */ + rx_tl = dev->rx_outstanding; + if (dev->msg_write_idx < dev->msgs_num) + rx_tl = min_t(int, rx_tl, dev->rx_fifo_depth / 2); + + regmap_write(dev->map, DW_IC_RX_TL, rx_tl ? rx_tl - 1 : 0); + __i2c_dw_write_intr_mask(dev, intr_mask); } base-commit: 04e9bf1648f846976b543e91c1838a712433772a