From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from sender6-op-o11.zoho.com (sender6-op-o11.zoho.com [165.173.180.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DCBC3290D1 for ; Wed, 7 Oct 2026 23:44:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.180.11 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791416688; cv=pass; b=JmPqSGyY8WQUgyjg2uA70Mn4hESIymZvSZ90n/2yQoh0aCu2O3pnGPajygCV/HgsM3JUSsVAZ2YnNbOc65P0ONbD5yso5o8veZkQc61bN5i3d9ULyJXvCHpTu3CqcmTQpWvu+40iACkhiuVm2OhGi/hQG5M3r2zo5cpkcfvpbUA= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791416688; c=relaxed/simple; bh=c7X8b74ywjqaJw1xMOJ/QyyXlM602ll9atW8Djb3EBY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WPqDHel4z0rMsATgxERr4PtK+7Es+5sn7LUafSHRBauV+FQF8l4/CU7TW0KQwG7xpjdSD8wA7rcWUrE/zF7IV519A5XNDPZ/yY4CQmyoyr8TTU52ftLjVrt9Vq+7t371VEww9ePc2gVXGAiWsXMrbmkK/1MYOLgx85yYW1WB6pk= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=adrian.larumbe@collabora.com header.b=SerBahc6; arc=pass smtp.client-ip=165.173.180.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=adrian.larumbe@collabora.com header.b="SerBahc6" ARC-Seal: i=1; a=rsa-sha256; t=1791416668; cv=none; d=zohomail.com; s=zohoarc; b=Plv+4OSeU5+/BjW9W23/4Nnuk+BY7oh34WMY+F49F143v0MKVqBiWZPS+2+9h8xlhRjl8oaQVfR0Z2KJ945+XOjehMvpn9fv5GeNIiEyojzm/uykpVO/v4lU37e7kW6Aia9KpVKgjVol59KgIL7WcGgRwW7HpOrLcRLJNbeSItc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791416668; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=tW7ZGdBI0CeTF9WeXr+7R/B9XC2tuQnNlaOB3VCmv/E=; b=IHLdPnuMW7aZ9BCnUhKKnTQXp/P5BRCkCV0YkEjn2BbPbc/7yvvoqBBT6PUOwBNh5Q0SPDz/MdvukqO9dgbwKbPhQt51VvkH9aHpWgcMDQqVwzpUSQrd4VVz3z2q9dIZGgoFOTKgSKxrQMXUWYai0QRwNc5OYshOjbuhwvKx7Jw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=adrian.larumbe@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1791416668; s=zohomail; d=collabora.com; i=adrian.larumbe@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=tW7ZGdBI0CeTF9WeXr+7R/B9XC2tuQnNlaOB3VCmv/E=; b=SerBahc6I9DllnGsoZDiZmu0kcEq4fZCPaz+aCZsDouNRmbWHsHIjTTD94SD/YGw EnSGSZwTQ9c9CtYQZB+YKOKCocD8YMJPf1pfCFVzrGLlY/DBEQOMxQS2lq/ULn683Eb kXZTWecrSq+hZIUl0NJnCMajxTuDFMqYs2oMEMGY= Received: by smtp.zohomail.com with SMTPS id 1791416667760477.24278749785094; Wed, 7 Oct 2026 16:44:27 -0700 (PDT) From: =?utf-8?q?Adri=C3=A1n_Larumbe?= Date: Thu, 08 Oct 2026 00:42:57 +0100 Subject: [PATCH v13 14/15] drm/panfrost: Introduce a reset lock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20261008-claude-fixes-v13-14-d6a493185860@collabora.com> References: <20261008-claude-fixes-v13-0-d6a493185860@collabora.com> In-Reply-To: <20261008-claude-fixes-v13-0-d6a493185860@collabora.com> To: Boris Brezillon , Rob Herring , Steven Price , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Faith Ekstrand , "Marty E. Plummer" , Tomeu Vizoso , Eric Anholt , Robin Murphy , Philipp Zabel Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Collabora Kernel Team , =?utf-8?q?Adri=C3=A1n_Larumbe?= , Neil Armstrong X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3054; i=adrian.larumbe@collabora.com; h=from:subject:message-id; bh=c7X8b74ywjqaJw1xMOJ/QyyXlM602ll9atW8Djb3EBY=; b=owEB7QES/pANAwAKAQ4mfkzuU0M9AcsmYgBqxtj74icApE0i4+ky7Vm+NUkNiIwf78LoG70wl iZqfgQjh3WJAbMEAAEKAB0WIQQyQDDowAUXXfk3B6QOJn5M7lNDPQUCasbY+wAKCRAOJn5M7lND PRbIC/9XRD8kt8zR8Pdq5IJOMyjJG/sMVHdYHcM5cZrcSRFJrMQ3obIwPkn27CBfRdpnIhnTQbr AcEfIRWT4zhVX0N51e2UWbjXcZGe0oiZ7fiCIBrifNyyOtNPT4ly774K0VXx0P5qradFwqYQUma NFsHxjnBO52AJasiUGmxvXRsTV7sWatxTx5TFf2LmNHn0euP0puN/zjBMsrZPvRY0rHD6FO3aUv 4LgOqHo4J9IkC6BKeB7L03O8Rx3Trl72t1AjnlUn3cerqe7uGO4thFi/fDG4xzIu7UCgwLqIvKl 9ELKEWlij5UNC2ILbKEY7XBYzhTKOKEIA+9Et2ru4Oky1h8J0mnfpmrDjMBcSvX9XT5urBY4bAD U+Juan9cqSAc2GgWgfaBZaUJ9wWKvtvMRBqUG0EqQRSFKRBUlv13i/ubAD1q6BwckIbAQWeHAGw SAa6DzjYDOs6IFTZ73q1oHeXWLc9fF5JR7clnHssZH6xvP49BwxuWeWxJu8feXljX0EZg= X-Developer-Key: i=adrian.larumbe@collabora.com; a=openpgp; fpr=324030E8C005175DF93707A40E267E4CEE53433D In order to avoid accessing HW register while a reset is ongoing, a read/write semaphore that envelopes the reset sequence will help driver entry points avoid racing with it. For now, the only such racy entry point is the ioctl that returns the current GPU timestamp. Reviewed-by: Boris Brezillon Reviewed-by: Steven Price Signed-off-by: Adrián Larumbe --- drivers/gpu/drm/panfrost/panfrost_device.c | 2 ++ drivers/gpu/drm/panfrost/panfrost_device.h | 1 + drivers/gpu/drm/panfrost/panfrost_drv.c | 9 ++++++--- drivers/gpu/drm/panfrost/panfrost_job.c | 1 + 4 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c index b3dae6ce3eb0..5718e8185427 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -509,6 +509,8 @@ bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev, void panfrost_device_reset(struct panfrost_device *pfdev, bool enable_job_int) { + guard(rwsem_write)(&pfdev->reset.lock); + panfrost_gpu_soft_reset(pfdev); panfrost_gpu_power_on(pfdev); diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h index a0b9a2145fc9..63452febb1cf 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -165,6 +165,7 @@ struct panfrost_device { struct { struct workqueue_struct *wq; struct work_struct work; + struct rw_semaphore lock; atomic_t pending; } reset; diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c index f77780c72a1a..571a26b84126 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -41,9 +41,12 @@ static int panfrost_ioctl_query_timestamp(struct panfrost_device *pfdev, if (ret) return ret; - panfrost_cycle_counter_get(pfdev); - *arg = panfrost_timestamp_read(pfdev); - panfrost_cycle_counter_put(pfdev); + /* We should not read timestamp register while the GPU is being reset */ + scoped_guard(rwsem_read, &pfdev->reset.lock) { + panfrost_cycle_counter_get(pfdev); + *arg = panfrost_timestamp_read(pfdev); + panfrost_cycle_counter_put(pfdev); + } pm_runtime_put(pfdev->base.dev); return 0; diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c index ab65786bf63b..4ddf4b722ddf 100644 --- a/drivers/gpu/drm/panfrost/panfrost_job.c +++ b/drivers/gpu/drm/panfrost/panfrost_job.c @@ -877,6 +877,7 @@ int panfrost_jm_init(struct panfrost_device *pfdev) INIT_WORK(&pfdev->reset.work, panfrost_reset_work); spin_lock_init(&js->job_lock); mutex_init(&pfdev->sched_lock); + init_rwsem(&pfdev->reset.lock); js->irq = platform_get_irq_byname(to_platform_device(pfdev->base.dev), "job"); if (js->irq < 0) -- 2.55.0