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However, these limits are not hardware limits meaning that a single LM can support higher resolutions. Switch to basing LM reservation off of PINGPONG and DSC encoder hardware limits. This revision also adds clock-based mixer selection and a source-pipe width guard for mixers without source split. Assisted-by: LLM Signed-off-by: Mahadevan P --- Changes in v4: - Rebased on msm-next, resolving conflicts. - Added clock-based mixer selection and reused the helper in mode validation. - Added a source-pipe width guard for mixers without source split. - Extended the catalog cleanup to newer platforms. - Link to v3: https://lore.kernel.org/r/20260112-max-mixer-width-v3-0-f98063ea21f5@oss.qualcomm.com Changes in v3: - Rebased on msm-next, fixing conflicts - Updated commit messages to describe the actual issue. - Link to v2: https://lore.kernel.org/r/20260103-max-mixer-width-v2-0-ef5d3d246709@oss.qualcomm.com Changes in v2: - Dropped PP and DSC encoder width drop the catalog, they are now determined in the code by using the DPU programming - Corrected DSC encoder width for DPUs < 8.x (2048 vs 2560) - Link to v1: https://lore.kernel.org/r/20250514-max-mixer-width-v1-0-c8ba0d9bb858@oss.qualcomm.com --- Jessica Zhang (3): drm/msm/dpu: check mode against PINGPONG or DSC max width drm/msm/dpu: filter writeback modes using writeback maxlinewidth drm/msm/dpu: remove max_mixer_width from catalog Mahadevan P (3): drm/msm/dpu: split modes a single layer mixer cannot clock drm/msm/dpu: do not assume a merged datapath when validating mode clock drm/msm/dpu: limit the mode width to a pipe if the LM has no source split .../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 1 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 1 - .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 82 +++++++++++++++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 9 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c | 9 +-- 36 files changed, 79 insertions(+), 54 deletions(-) --- base-commit: aac26bee2287c88af5be5a5ff96d783b19a28790 change-id: 20261008-lm_fixes_final-9b9a8d0d9835 Best regards, -- Mahadevan P