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a=ed25519-sha256; t=1791480250; l=2937; i=mahadevan.p@oss.qualcomm.com; s=20250923; h=from:subject:message-id; bh=MnyWJ+SO3iVE/KBDqM+VhT8LcMf8ChXq7BB83zMO3hk=; b=4c6pDXhR1kZ5t5q72Ly3Q/VqiVwkXneHI9x6vfrwARO/BKVLjo3GdiTa1UiLNQQnZtdisKxtN 4Ry5ZxmvsfyCxnAq8C/gzrgTzC4M0U+1yjdLDCaxJeNqNYcYLFqzRF9 X-Developer-Key: i=mahadevan.p@oss.qualcomm.com; a=ed25519; pk=wed9wuAek0VbCYfkANx7ujIG4VY0XfCYrffFKPN2p0Y= X-Proofpoint-ORIG-GUID: pLzZ9ZOu41GITPAxa5FXr-7rGDi4_KU4 X-Authority-Analysis: v=2.4 cv=U98Hnuru c=1 sm=1 tr=0 ts=6ac7d1c6 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=hBLlU2GVctrw3cDPktIA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA4MDA2OSBTYWx0ZWRfX1tWLjTPc+Oez H2kbqtqWvBnmSSl90PfRTnwL3+oNhGtmGEZJ9rdelVEDX1mQY8SSW2mzl2duuQ/1sr+b6pRoHVG hBnrJm6mCCPAf1AappcejmFN0TIhCio= X-Proofpoint-GUID: pLzZ9ZOu41GITPAxa5FXr-7rGDi4_KU4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA4MDA2OSBTYWx0ZWRfXwygbf3eJc/mW xHrZPwznTXDuLkKyEa6MEYgnsgkowEfkKFMlN3Ab41EWn1RpOm6BxO3BTlYg09Nfq9boFdtOevw YpZ4PJAuUFyaQuWr+6ggP1epea/OhKlA5LMVajHIej9qEwHBh1v8dqQ4Oj0N/NiTdPExlKDJjt2 TEtMwu6DgWes5WTEW5p267nrI+VbAHAyB2Tggm2mpM9QNnEVod1M1CzfaJA8L5n6o4DxvF5Oo0U Fpra5eju1EVeKgiU1IhaRW8XcopigL08uzuhC3rFp0saAf/cTZB9KBD+O3ONJFL8SlQes49rt1+ x625rqLSsy3vF9uoulrcL61LfIV50HOKXAN7nYJYXdFuBZKxUltBTfqLZR/yTVV5FO68ip0/gtF mp5shROU8hVFvqEPDnLrqhCjHSH/0qBKDBrmpOAvU1SWyxytQiiTvJ/xt0IZ0zYZ9yNuAeJtsHR ECnTsu/6W8AxI8H6+/Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-08_05,2026-10-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610080069 The layer mixer count is picked purely from the mode width, via the MAX_HDISPLAY_SPLIT threshold. Width is only half of what constrains a mixer: it also processes one pixel per core clock cycle, so a mode narrow enough to stay under the width threshold can still demand a higher pixel rate than one mixer sustains. A 1080 wide panel at a few hundred Hz is enough to get there. Such a mode is currently given a single mixer and then has to be clocked past the maximum core clock rate, which that mixer cannot do. Factor the decision out into dpu_crtc_num_lm_for_mode() and have it ask for a second mixer when the adjusted mode clock does not fit the maximum core clock rate, in addition to the existing width test. Modes that already fit within one mixer are unaffected, so the only decisions that change are the ones that could not be driven as they were. Assisted-by: LLM Signed-off-by: Mahadevan P --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 77a2d1f6700d..0b51a4c5db57 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1376,6 +1376,25 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state #define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE #define MAX_HDISPLAY_SPLIT 1080 +static u32 dpu_crtc_num_lm_for_mode(struct dpu_kms *dpu_kms, + const struct drm_display_mode *mode) +{ + u64 mode_clk; + + if (!dpu_kms->catalog->caps->has_3d_merge) + return 1; + + if (mode->hdisplay > MAX_HDISPLAY_SPLIT) + return 2; + + mode_clk = dpu_core_perf_adjusted_mode_clk(mode->clock, + dpu_kms->perf.perf_cfg); + if (mode_clk * 1000 > dpu_kms->perf.max_core_clk_rate) + return 2; + + return 1; +} + static struct msm_display_topology dpu_crtc_get_topology( struct drm_crtc *crtc, struct dpu_kms *dpu_kms, @@ -1409,8 +1428,8 @@ static struct msm_display_topology dpu_crtc_get_topology( * enabled. This is because in cases where CWB is enabled, num_intf will * count both the WB and real-time phys encoders. * - * For non-DSC CWB usecases, have the num_lm be decided by the - * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check. + * For non-DSC CWB usecases, have the num_lm be decided by + * dpu_crtc_num_lm_for_mode(). */ if (topology.num_intf == 2 && !topology.cwb_enabled) @@ -1419,7 +1438,7 @@ static struct msm_display_topology dpu_crtc_get_topology( topology.num_lm = 2; else if (dpu_kms->catalog->caps->has_3d_merge && topology.num_dsc == 0) - topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; + topology.num_lm = dpu_crtc_num_lm_for_mode(dpu_kms, mode); else topology.num_lm = 1; -- 2.34.1