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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF000037AC.mail.protection.outlook.com (10.167.244.186) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.496.14 via Frontend Transport; Thu, 8 Oct 2026 03:24:12 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Wed, 7 Oct 2026 22:24:03 -0500 Received: from xsjdavidzha51.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Wed, 7 Oct 2026 22:24:02 -0500 From: David Zhang To: , , , , , , CC: David Zhang , , , Nishad Saraf Subject: [PATCH V3 09/19] accel/amdxdna: Add context switch hysteresis with debugfs control Date: Wed, 7 Oct 2026 20:23:38 -0700 Message-ID: <20261008032348.2044667-10-yidong.zhang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261008032348.2044667-1-yidong.zhang@amd.com> References: <20261008032348.2044667-1-yidong.zhang@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000037AC:EE_|MW6PR12MB8758:EE_ X-MS-Office365-Filtering-Correlation-Id: c22da9b4-aafa-4d91-9c80-08df24eb9f76 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|23010399003|36860700016|1800799024|82310400026|56012099006|11063799006|4143699003|10067099003|22082099003|6133799003|18002099003; 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Expose a debugfs node 'ctx_switch_hysteresis_us' to change the timeout at runtime (0 disables hysteresis). The stored value is re-applied on every hw start so it survives runtime suspend/resume. Co-developed-by: Nishad Saraf Signed-off-by: Nishad Saraf Signed-off-by: David Zhang --- drivers/accel/amdxdna/aie4_message.c | 43 +++++++++++++ drivers/accel/amdxdna/aie4_msg_priv.h | 24 +++++++ drivers/accel/amdxdna/aie4_pci.c | 83 ++++++++++++++++++++++++- drivers/accel/amdxdna/aie4_pci.h | 9 +++ drivers/accel/amdxdna/amdxdna_debugfs.c | 3 + drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 + 6 files changed, 161 insertions(+), 2 deletions(-) diff --git a/drivers/accel/amdxdna/aie4_message.c b/drivers/accel/amdxdna/aie4_message.c index 7112b0bc3725..fc0b498b2923 100644 --- a/drivers/accel/amdxdna/aie4_message.c +++ b/drivers/accel/amdxdna/aie4_message.c @@ -262,3 +262,46 @@ int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode) return ret; } + +int aie4_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, + const void *data, size_t size) +{ + DECLARE_AIE_MSG(aie4_msg_set_runtime_cfg, AIE4_MSG_OP_SET_RUNTIME_CONFIG); + u8 buf[sizeof(req.type) + AIE4_RUNTIME_CFG_MAX_DATA_SIZE] __aligned(4) = { 0 }; + int ret; + + if (size > AIE4_RUNTIME_CFG_MAX_DATA_SIZE) + return -EINVAL; + + /* Stage runtime config type and payload for firmware mailbox message. */ + req.type = type; + memcpy(buf, &req.type, sizeof(req.type)); + memcpy(buf + sizeof(req.type), data, size); + + msg.send_data = buf; + msg.send_size = sizeof(req.type) + size; + + ret = aie_send_mgmt_msg_wait(&ndev->aie, &msg); + if (ret) + XDNA_ERR(ndev->aie.xdna, "Failed to set runtime cfg %u: %d", type, ret); + return ret; +} + +int aie4_set_ctx_hysteresis(struct amdxdna_dev_hdl *ndev, u32 timeout_us) +{ + struct aie4_msg_runtime_config_ctx_switch_hysteresis cfg = { + .timeout_us = timeout_us, + }; + int ret; + + ret = aie4_set_runtime_cfg(ndev, AIE4_RUNTIME_CONFIG_CTX_SWITCH_HYSTERESIS, + &cfg, sizeof(cfg)); + if (ret) + XDNA_WARN(ndev->aie.xdna, + "Failed to set ctx switch hysteresis to %u us (%d), using fw default", + timeout_us, ret); + else + XDNA_DBG(ndev->aie.xdna, "Context switch hysteresis set to %u us", timeout_us); + + return ret; +} diff --git a/drivers/accel/amdxdna/aie4_msg_priv.h b/drivers/accel/amdxdna/aie4_msg_priv.h index fe78df9e23c8..636bf8d04c76 100644 --- a/drivers/accel/amdxdna/aie4_msg_priv.h +++ b/drivers/accel/amdxdna/aie4_msg_priv.h @@ -12,6 +12,7 @@ enum aie4_msg_opcode { AIE4_MSG_OP_IDENTIFY = 0x10002, AIE4_MSG_OP_SUSPEND = 0x10003, + AIE4_MSG_OP_SET_RUNTIME_CONFIG = 0x10007, AIE4_MSG_OP_QUERY_CERT_FIRMWARE_VERSION = 0x1000F, AIE4_MSG_OP_CREATE_VFS = 0x20001, @@ -65,6 +66,29 @@ struct aie4_msg_suspend_resp { enum aie4_msg_status status; } __packed; +/* Type selector for AIE4_MSG_OP_SET_RUNTIME_CONFIG. */ +enum aie4_msg_runtime_config_type { + AIE4_RUNTIME_CONFIG_CTX_SWITCH_HYSTERESIS = 0xD, + AIE4_MAX_RUNTIME_CONFIG +}; + +struct aie4_msg_set_runtime_cfg_req { + __u32 type; + __u8 data[4]; +} __packed; + +struct aie4_msg_set_runtime_cfg_resp { + enum aie4_msg_status status; +} __packed; + +/* Maximum payload for runtime config firmware message. */ +#define AIE4_RUNTIME_CFG_MAX_DATA_SIZE 16 + +/* Context switch hysteresis timeout in microseconds (0 disables). */ +struct aie4_msg_runtime_config_ctx_switch_hysteresis { + __u32 timeout_us; +} __packed; + struct aie4_msg_create_vfs_req { __u32 vf_cnt; } __packed; diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c index fdcf6b8602e9..d051aa1b51e6 100644 --- a/drivers/accel/amdxdna/aie4_pci.c +++ b/drivers/accel/amdxdna/aie4_pci.c @@ -5,8 +5,10 @@ #include #include +#include #include #include +#include #include #include @@ -321,6 +323,22 @@ int aie4_restore_power_mode(struct amdxdna_dev_hdl *ndev) return aie4_msg_set_power_mode(ndev, ndev->pw_mode); } +static int aie4_config_fw(struct amdxdna_dev_hdl *ndev) +{ + int ret; + + ret = aie4_attach_work_buffer(ndev); + if (ret) + return ret; + + /* Best-effort tuning knob; failure is warned inside and does not fail hw start */ + ret = aie4_set_ctx_hysteresis(ndev, ndev->ctx_switch_hysteresis_us); + if (ret == -ETIME) + return ret; + + return 0; +} + static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev) { int ret; @@ -333,7 +351,7 @@ static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev) if (ret) goto stop_fw; - ret = aie4_attach_work_buffer(ndev); + ret = aie4_config_fw(ndev); if (ret) goto mbox_fini; @@ -417,7 +435,7 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev) if (ret) goto mailbox_fini; - ret = aie4_attach_work_buffer(ndev); + ret = aie4_config_fw(ndev); if (ret) goto mailbox_fini; @@ -572,6 +590,7 @@ static int aie4m_pcidev_init(struct amdxdna_dev *xdna) ndev->priv = xdna->dev_info->dev_priv; ndev->aie.xdna = xdna; + ndev->ctx_switch_hysteresis_us = AIE4_CTX_HYSTERESIS_US; ndev->pw_mode = POWER_MODE_DEFAULT; xdna->dev_handle = ndev; @@ -917,15 +936,74 @@ static void aie4_classic_fini(struct amdxdna_dev *xdna) aie4_free_work_buffer(xdna->dev_handle); } +static int aie4_ctx_hysteresis_get(void *data, u64 *val) +{ + struct amdxdna_dev_hdl *ndev = data; + struct amdxdna_dev *xdna = ndev->aie.xdna; + + guard(mutex)(&xdna->dev_lock); + *val = ndev->ctx_switch_hysteresis_us; + + return 0; +} + +static int aie4_ctx_hysteresis_set(void *data, u64 val) +{ + struct amdxdna_dev_hdl *ndev = data; + struct amdxdna_dev *xdna = ndev->aie.xdna; + int ret, idx; + + if (val > U32_MAX) + return -EINVAL; + + if (!drm_dev_enter(&xdna->ddev, &idx)) + return -ENODEV; + + mutex_lock(&xdna->dev_lock); + + ret = amdxdna_pm_resume_get_locked(xdna); + if (ret) + goto unlock; + + ret = aie4_set_ctx_hysteresis(ndev, (u32)val); + if (!ret) + ndev->ctx_switch_hysteresis_us = (u32)val; + + amdxdna_pm_suspend_put(xdna); + +unlock: + mutex_unlock(&xdna->dev_lock); + drm_dev_exit(idx); + + return ret; +} + +/* Context switch hysteresis timeout in microseconds; 0 disables hysteresis. */ +DEFINE_DEBUGFS_ATTRIBUTE(aie4_ctx_hysteresis_fops, aie4_ctx_hysteresis_get, + aie4_ctx_hysteresis_set, "%llu\n"); + +static void aie4_debugfs_init(struct amdxdna_dev *xdna) +{ + struct amdxdna_dev_hdl *ndev = xdna->dev_handle; + + /* Context switch hysteresis is only supported on PF and classic devices. */ + if (!to_pci_dev(xdna->ddev.dev)->is_virtfn) + debugfs_create_file_unsafe("ctx_switch_hysteresis_us", 0600, + xdna->ddev.accel->debugfs_root, ndev, + &aie4_ctx_hysteresis_fops); +} + const struct amdxdna_dev_ops aie4_pf_ops = { .init = aie4_pf_init, .fini = aie4_pf_fini, + .debugfs_init = aie4_debugfs_init, .sriov_configure = aie4_sriov_configure, }; const struct amdxdna_dev_ops aie4_vf_ops = { .init = aie4_vf_init, .fini = aie4_vf_fini, + .debugfs_init = aie4_debugfs_init, .hwctx_init = aie4_hwctx_init, .hwctx_fini = aie4_hwctx_fini, .cmd_wait = aie4_cmd_wait, @@ -936,6 +1014,7 @@ const struct amdxdna_dev_ops aie4_vf_ops = { const struct amdxdna_dev_ops aie4_classic_ops = { .init = aie4_classic_init, .fini = aie4_classic_fini, + .debugfs_init = aie4_debugfs_init, .hwctx_init = aie4_hwctx_init, .hwctx_fini = aie4_hwctx_fini, .cmd_wait = aie4_cmd_wait, diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h index 6e9e7f874a44..959ef3695813 100644 --- a/drivers/accel/amdxdna/aie4_pci.h +++ b/drivers/accel/amdxdna/aie4_pci.h @@ -14,6 +14,9 @@ #include "aie4_msg_priv.h" #include "amdxdna_mailbox.h" +/* Default context switch hysteresis timeout in microseconds. */ +#define AIE4_CTX_HYSTERESIS_US 1000 + struct cert_comp { struct amdxdna_dev_hdl *ndev; u32 msix_idx; @@ -69,6 +72,9 @@ struct amdxdna_dev_hdl { u8 pw_mode; + /* Context switch hysteresis timeout in microseconds. */ + u32 ctx_switch_hysteresis_us; + struct amdxdna_drm_query_firmware_version cert_version; }; @@ -92,6 +98,9 @@ int aie4_init_dpm_freq_table(struct amdxdna_dev_hdl *ndev); int aie4_query_dpm_level(struct amdxdna_dev_hdl *ndev, u32 *aieclk_dpm_level, u32 *npuhclk_dpm_level); int aie4_msg_set_power_mode(struct amdxdna_dev_hdl *ndev, u8 power_mode); +int aie4_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, + const void *data, size_t size); +int aie4_set_ctx_hysteresis(struct amdxdna_dev_hdl *ndev, u32 timeout_us); u32 aie4_msg_pasid(struct amdxdna_client *client); /* aie4_ctx.c */ diff --git a/drivers/accel/amdxdna/amdxdna_debugfs.c b/drivers/accel/amdxdna/amdxdna_debugfs.c index a6ec17c63629..1f63cc91b168 100644 --- a/drivers/accel/amdxdna/amdxdna_debugfs.c +++ b/drivers/accel/amdxdna/amdxdna_debugfs.c @@ -126,4 +126,7 @@ void amdxdna_debugfs_init(struct amdxdna_dev *xdna) xdna, amdxdna_dbgfs_files[i].fops); } + + if (xdna->dev_info->ops->debugfs_init) + xdna->dev_info->ops->debugfs_init(xdna); } diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h index 953bf783b3f7..11f46ec738d7 100644 --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h @@ -54,6 +54,7 @@ struct amdxdna_sched_job; struct amdxdna_dev_ops { int (*init)(struct amdxdna_dev *xdna); void (*fini)(struct amdxdna_dev *xdna); + void (*debugfs_init)(struct amdxdna_dev *xdna); int (*resume)(struct amdxdna_dev *xdna); int (*suspend)(struct amdxdna_dev *xdna); int (*sriov_configure)(struct amdxdna_dev *xdna, int num_vfs); -- 2.34.1