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From: David Zhang <yidong.zhang@amd.com>
To: <quic_jhugo@quicinc.com>, <karol.wachowski@linux.intel.com>,
	<max.zhen@amd.com>, <lizhi.hou@amd.com>, <ogabbay@kernel.org>,
	<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>
Cc: David Zhang <yidong.zhang@amd.com>, <sonal.santan@amd.com>,
	<mario.limonciello@amd.com>, Wendy Liang <wendy.liang@amd.com>
Subject: [PATCH V3 13/19] accel/amdxdna: Prepare for AIE4 command submission
Date: Wed, 7 Oct 2026 20:23:42 -0700	[thread overview]
Message-ID: <20261008032348.2044667-14-yidong.zhang@amd.com> (raw)
In-Reply-To: <20261008032348.2044667-1-yidong.zhang@amd.com>

Prepare the data structures and completion wait helpers required for
AIE4 command submission:
- Define struct amdxdna_cmd_start_dpu in amdxdna_ctx.h for the
  ERT_START_DPU payload.
- Extend union amdxdna_job_priv with an aie4 member for queue list
  linkage and job state tracking.
- Implement smp_rmb() ordering and non-sleeping retry in
  get_read_index(), returning zero (no completion) when the sample
  is still invalid after the retry.
- Update check_cmd_done() and aie4_cmd_wait() to detect asynchronous
  device disconnect and reset via check_cert_comp_linked().

get_read_index() returns 0 for an invalid sample. Since 0 <= any
sequence number, callers never treat it as a completion. If this
happens while the context is disconnected, aie4_cmd_wait() returns
-EAGAIN so the caller retries the wait until a valid read_index is
observed; the command state and fence are not affected.

Co-developed-by: Max Zhen <max.zhen@amd.com>
Signed-off-by: Max Zhen <max.zhen@amd.com>
Co-developed-by: Wendy Liang <wendy.liang@amd.com>
Signed-off-by: Wendy Liang <wendy.liang@amd.com>
Signed-off-by: David Zhang <yidong.zhang@amd.com>
---
 drivers/accel/amdxdna/aie4_ctx.c    | 58 ++++++++++++++++++++---------
 drivers/accel/amdxdna/amdxdna_ctx.h | 20 ++++++++++
 2 files changed, 60 insertions(+), 18 deletions(-)

diff --git a/drivers/accel/amdxdna/aie4_ctx.c b/drivers/accel/amdxdna/aie4_ctx.c
index 226570367f71..09c92b1b5134 100644
--- a/drivers/accel/amdxdna/aie4_ctx.c
+++ b/drivers/accel/amdxdna/aie4_ctx.c
@@ -394,34 +394,46 @@ static inline bool valid_queue_index(u64 read, u64 write, u32 capacity)
 
 static u64 get_read_index(struct amdxdna_hwctx *hwctx)
 {
-	u64 wi = READ_ONCE(*hwctx->priv->umq_write_index);
-	u64 ri = READ_ONCE(*hwctx->priv->umq_read_index);
+	struct amdxdna_hwctx_priv *priv = hwctx->priv;
 	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	u64 ri, wi;
+
+	/* Sample read_index before write_index to guarantee wi >= ri. */
+	ri = READ_ONCE(*priv->umq_read_index);
+	/* Order the read_index sample before the write_index sample. */
+	smp_rmb();
+	wi = READ_ONCE(priv->write_index);
 
-	/*
-	 * CERT cannot update read index as uint64 atomically. Driver may read
-	 * half-updated read index when it has bits in high 32bit. In case read
-	 * index is not valid, wait for some time and retry once. It should
-	 * allow CERT to complete the read index update.
-	 */
+	/* Non-atomic 64-bit counter update by CERT; re-sample once if invalid. */
 	if (!valid_queue_index(ri, wi, CTX_MAX_CMDS)) {
-		XDNA_WARN(xdna, "Invalid index, ri %llu, wi %llu", ri, wi);
-		usleep_range(100, 200);
-		ri = READ_ONCE(*hwctx->priv->umq_read_index);
+		ri = READ_ONCE(*priv->umq_read_index);
+		/* Order the read_index sample before the write_index sample. */
+		smp_rmb();
+		wi = READ_ONCE(priv->write_index);
 		if (!valid_queue_index(ri, wi, CTX_MAX_CMDS)) {
-			XDNA_ERR(xdna, "Invalid index after retry, ri %llu, wi %llu", ri, wi);
-			ri = 0;
+			/* 0 <= any seq: callers always treat it as "not done" and retry. */
+			XDNA_DBG(xdna, "Invalid index, ri %llu, wi %llu", ri, wi);
+			return 0;
 		}
 	}
 
 	return ri;
 }
 
-static inline bool check_cmd_done(struct amdxdna_hwctx *hwctx, u64 seq)
+/* Verify cert_comp remains linked to detect disconnect or reset. */
+static bool check_cert_comp_linked(struct amdxdna_hwctx *hwctx, struct cert_comp *comp)
+{
+	/* READ_ONCE pairs with the link/unlink WRITE_ONCE. */
+	return comp == READ_ONCE(hwctx->priv->cert_comp);
+}
+
+static inline bool check_cmd_done(struct amdxdna_hwctx *hwctx, u64 seq, struct cert_comp *comp)
 {
-	u64 read_idx = get_read_index(hwctx);
+	/* Lockless check for wait_event condition; detects completion or disconnect. */
+	if (!check_cert_comp_linked(hwctx, comp))
+		return true;
 
-	return read_idx > seq;
+	return get_read_index(hwctx) > seq;
 }
 
 int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
@@ -437,11 +449,21 @@ int aie4_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq, u32 timeout)
 		wait_jifs = msecs_to_jiffies(timeout);
 
 	ret = wait_event_interruptible_timeout(cert_comp->waitq,
-					       (check_cmd_done(hwctx, seq)),
+					       check_cmd_done(hwctx, seq, cert_comp),
 					       wait_jifs);
 
-	if (!ret)
+	if (!ret) {
 		ret = -ETIME;
+	} else if (ret > 0 && !check_cert_comp_linked(hwctx, cert_comp) &&
+		   get_read_index(hwctx) <= seq) {
+		/*
+		 * Disconnected, or read_index invalid (0), before completion was
+		 * seen. -EAGAIN is by design: the caller retries the wait until a
+		 * valid read_index is observed. Command state and fence are not
+		 * affected.
+		 */
+		ret = -EAGAIN;
+	}
 
 	aie4_put_cert_comp(cert_comp);
 
diff --git a/drivers/accel/amdxdna/amdxdna_ctx.h b/drivers/accel/amdxdna/amdxdna_ctx.h
index 9bbc3db4ebde..b3677851d1c5 100644
--- a/drivers/accel/amdxdna/amdxdna_ctx.h
+++ b/drivers/accel/amdxdna/amdxdna_ctx.h
@@ -48,6 +48,18 @@ struct amdxdna_cmd_start_npu {
 	u32 prop_args[];  /* properties and regular kernel arguments */
 };
 
+/*
+ * struct amdxdna_cmd_start_dpu - interpretation of data payload for
+ * ERT_START_DPU in amdxdna_cmd.
+ */
+struct amdxdna_cmd_start_dpu {
+	u64 dtrace_buffer;		/* dtrace buffer address 2 words */
+	u64 instruction_buffer;		/* buffer address 2 words */
+	u32 instruction_buffer_size;	/* size of buffer in bytes */
+	u16 uc_index;			/* microblaze controller index */
+	u16 chained;			/* number of following amdxdna_cmd_start_dpu elements */
+};
+
 /*
  * Interpretation of the beginning of data payload for ERT_CMD_CHAIN in
  * amdxdna_cmd. The rest of the payload in amdxdna_cmd is cmd BO handles.
@@ -138,8 +150,14 @@ struct amdxdna_drv_cmd {
 };
 
 struct app_health_report;
+
 union amdxdna_job_priv {
 	struct app_health_report *aie2_health;
+	/* aie4 kernel submission: queue linkage + job state */
+	struct {
+		struct list_head	list;
+		u32			state;
+	} aie4;
 };
 
 struct amdxdna_sched_job {
@@ -162,6 +180,8 @@ struct amdxdna_sched_job {
 };
 
 #define aie2_job_health priv.aie2_health
+#define aie4_job_list	priv.aie4.list
+#define aie4_job_state	priv.aie4.state
 
 static inline u32
 amdxdna_cmd_get_op(struct amdxdna_gem_obj *abo)
-- 
2.34.1


  parent reply	other threads:[~2026-10-08  3:24 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-08  3:23 [PATCH V3 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
2026-10-08  3:23 ` [PATCH V3 01/19] accel/amdxdna: Rename NPU3 firmware files David Zhang
2026-10-08 16:23   ` Lizhi Hou
2026-10-08  3:23 ` [PATCH V3 02/19] accel/amdxdna: Remove mmap for doorbell David Zhang
2026-10-08  3:23 ` [PATCH V3 03/19] accel/amdxdna: Add CERT firmware version support David Zhang
2026-10-08 17:12   ` Lizhi Hou
2026-10-08 17:26     ` Zhang, Yidong (David)
2026-10-08  3:23 ` [PATCH V3 04/19] accel/amdxdna: Upgrade firmware version to 6.0 David Zhang
2026-10-08 17:15   ` Lizhi Hou
2026-10-08  3:23 ` [PATCH V3 05/19] accel/amdxdna: Add NPU3 classic device support David Zhang
2026-10-08  3:23 ` [PATCH V3 06/19] accel/amdxdna: Add AIE version query to aie4_get_info David Zhang
2026-10-08  3:23 ` [PATCH V3 07/19] accel/amdxdna: Add get and set power_mode for AIE4 David Zhang
2026-10-08  3:23 ` [PATCH V3 08/19] accel/amdxdna: Add clock, DPM frequency, and resource info queries " David Zhang
2026-10-08  3:23 ` [PATCH V3 09/19] accel/amdxdna: Add context switch hysteresis with debugfs control David Zhang
2026-10-08  3:23 ` [PATCH V3 10/19] accel/amdxdna: Refactor AIE4 hardware initialization sequence David Zhang
2026-10-08  3:23 ` [PATCH V3 11/19] accel/amdxdna: Decouple AIE4 doorbell and MSI-X notify transport hooks David Zhang
2026-10-08  3:23 ` [PATCH V3 12/19] accel/amdxdna: Implement AIE4 kernel queue lifecycle and memory layout David Zhang
2026-10-08  3:23 ` David Zhang [this message]
2026-10-08  3:23 ` [PATCH V3 14/19] accel/amdxdna: Move HMM invalidate wait into common GEM code David Zhang
2026-10-08  3:23 ` [PATCH V3 15/19] accel/amdxdna: Make populate_range common for AIE2 and AIE4 David Zhang
2026-10-08  3:23 ` [PATCH V3 16/19] accel/amdxdna: Implement AIE4 command packet building and submission David Zhang
2026-10-08  3:23 ` [PATCH V3 17/19] accel/amdxdna: Enable AIE4 firmware logging to DRAM David Zhang
2026-10-08  3:23 ` [PATCH V3 18/19] accel/amdxdna: Implement AIE4 suspend and resume David Zhang
2026-10-08  3:23 ` [PATCH V3 19/19] accel/amdxdna: Implement runtime suspend and resume support David Zhang

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