[PATCH 2/2] ARM: dts: imx6qdl-phytec-mira: Switch LVDS panel to 18-bit data mapping

[Primoz Fiser <primoz.fiser@norik.com>]

The phyBOARD-Mira drives its LVDS panel at 18 bits per pixel. This was
previously done by always overriding fsl,data-width on the LDB bridge
alone and leaving the panel node's compatible, "auo,g104sn02", resulting
in LDB and the panel disagreeing on the format actually in use.

Now, declare the override on the panel side too, via the data-mapping
property and use "jeida-18" which resolves to RGB666_1X7X3_SPWG, exactly
matching what fsl,data-mapping = "spwg" + fsl,data-width = <18> produces
on the LDB side. Both ends of the link are now consistent instead of
silently disagreeing.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
index 8b2b4ed76328..50e5bb22b9f5 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
@@ -121,6 +121,7 @@ panel {
 		power-supply = <&reg_panel>;
 		enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
 		backlight = <&backlight>;
+		data-mapping = "jeida-18";
 
 		port {
 			panel_in: endpoint {
@@ -204,7 +205,7 @@ &ldb {
 
 	lvds-channel@0 {
 		fsl,data-mapping = "spwg";
-		fsl,data-width = <24>;
+		fsl,data-width = <18>;
 		status = "disabled";
 
 		port@4 {
-- 
2.34.1