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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-16166121f2asm14522277c88.4.2026.10.08.01.11.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Oct 2026 01:11:07 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Taniya Das , Jagadeesh Kona , Bryan O'Donoghue , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH v2 3/4] arm64: dts: qcom: sm8750: Fix videocc clock inputs Date: Thu, 8 Oct 2026 16:10:35 +0800 Message-ID: <20261008081036.3492003-4-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261008081036.3492003-1-shengchao.guo@oss.qualcomm.com> References: <20261008081036.3492003-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA4MDAzMiBTYWx0ZWRfX9JCmNj3FRbbK /cLsIqgfftTwHLW/DcHR99aavBCqVr8VmtXHoskad+UUdOieKzyUmW7tin2s47J1GmE0Mcejb5Y njKojb4DbBhl/KnfXWRukxjdMHNF9glutIxbWFvwS0VkO8biD7SC3pJFqjoDW44iBcy2THog+Tr t7FeoZ3lzfNigRXsohFdPAl3IOfy0DGUf3a5q0evEhqZwKmdHW71IbnUc7UlXiGwiE+exaPKyQZ Rxsm/YjbviLTxDoh6nhT8Kj4xHWtOuHuQOQUGZoDopPdxP0tsEaiWrwhcpAcjuWq7cxjHf28yHx GnrJ1wmqUWAq3HIRAz6ZV8NJk1lopc2ImRHf4gZGvXlOxOMTaLJta9lfe01HkgY5BSuDmec+yfz 3px6voR8/D3+hVOdyw11mRIAm258csJ+pd/8ZHdMD6oOFpdLEHQFpFYzyry0QjOsDuJPy3lz7po OwusNlcW/2usRr2UhAw== X-Proofpoint-GUID: 5QvSnbKj1tx3vPQ2iRZ6Wnnl-_NO7J9q X-Proofpoint-ORIG-GUID: 5QvSnbKj1tx3vPQ2iRZ6Wnnl-_NO7J9q X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA4MDAzMiBTYWx0ZWRfX0X3KzLAW5YvY 48EmOhuqxenhirsXz+2dRV4ScC0uIBQkkKc5K0w4RdnxErpRSaOKea114mY3hyIiUjeyXCv8oKz 0YZHmfebh0IDfxf9zr+B13UFAJ9WLrw= X-Authority-Analysis: v=2.4 cv=MPT1C8Zl c=1 sm=1 tr=0 ts=6ac7501d cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=PKgm7S4WkqlbYhXdoGMA:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-08_03,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 adultscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610080032 The video clock controller binding describes three clock inputs for SM8750: the board XO, the always-on board XO and the 32 kHz sleep clock. The videocc node instead passes the board XO and GCC_VIDEO_AHB_CLK, which is not an input of the controller. Pass bi_tcxo_ao_div2 and the board sleep clock in place of the AHB clock. No functional change, GCC_VIDEO_AHB_CLK is enabled independently of this node. Assisted-by: LLM Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index cf947acc5760..678e6e167bde 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3338,7 +3338,8 @@ videocc: clock-controller@aaf0000 { compatible = "qcom,sm8750-videocc"; reg = <0x0 0x0aaf0000 0x0 0x10000>; clocks = <&bi_tcxo_div2>, - <&gcc GCC_VIDEO_AHB_CLK>; + <&bi_tcxo_ao_div2>, + <&sleep_clk>; power-domains = <&rpmhpd RPMHPD_MMCX>, <&rpmhpd RPMHPD_MXC>; required-opps = <&rpmhpd_opp_low_svs>, -- 2.43.0