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Thu, 8 Oct 2026 12:34:01 +0000 From: Changhuang Liang To: Brian Masney , Jerome Brunet , Stephen Boyd , Philipp Zabel , Emil Renner Berthing Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Hal Feng , Changhuang Liang Subject: [PATCH v6 11/15] clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver Date: Thu, 8 Oct 2026 05:33:34 -0700 Message-Id: <20261008123338.11081-12-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261008123338.11081-1-changhuang.liang@starfivetech.com> References: <20261008123338.11081-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SHXPR01CA0017.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::26) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1268:EE_ X-MS-Office365-Filtering-Correlation-Id: 22fec09b-2843-4c9a-e2a3-08df25386e89 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|7416014|1800799024|23010399003|366016|18002099003|22082099003|10067099003|56012099006|38350700014; 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Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 10 ++ drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-per1.c | 162 ++++++++++++++++++ 3 files changed, 173 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per1.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index b2a05bbb450f..62727ce3aef3 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -83,6 +83,16 @@ config CLK_STARFIVE_JHB100_PER0 Say yes here to support the peripheral-0 clock controller on the StarFive JHB100 SoC. +config CLK_STARFIVE_JHB100_PER1 + bool "StarFive JHB100 peripheral-1 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER + default ARCH_STARFIVE + help + Say yes here to support the peripheral-1 clock controller + on the StarFive JHB100 SoC. + config CLK_STARFIVE_JHB100_SYS0 bool "StarFive JHB100 system-0 clock support" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 352717886295..279e0cdfc99b 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per1.c b/drivers/clk/starfive/clk-starfive-jhb100-per1.c new file mode 100644 index 000000000000..1f56563bc77e --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-per1.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 Peripheral-1 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include + +#include "clk-starfive-jh71x0.h" + +#define JHB100_PER1CLK_NUM_CLKS (JHB100_PER1CLK_MAIN_ICG_EN_UFS + 1) + +/* external clocks */ +#define JHB100_PER1CLK_PLL7 (JHB100_PER1CLK_NUM_CLKS + 0) +#define JHB100_PER1CLK_NCNOC_INIT (JHB100_PER1CLK_NUM_CLKS + 1) +#define JHB100_PER1CLK_CFG_800 (JHB100_PER1CLK_NUM_CLKS + 2) +#define JHB100_PER1CLK_NCNOC_TARG (JHB100_PER1CLK_NUM_CLKS + 3) +#define JHB100_PER1CLK_CFG_143 (JHB100_PER1CLK_NUM_CLKS + 4) + +static const char * const jhb100_per1_ext_clk[] = { + "pll7", + "ncnoc_init", + "cfg_800", + "ncnoc_targ", + "cfg_143", +}; + +/* + * Regarding the CLK_IS_CRITICAL flag: + * Clocks flagged CLK_IS_CRITICAL feed logic that has to keep running whether + * or not a consumer holds them, such as the bus interconnect and always-on + * blocks. Gating them hangs the system, so they must never be disabled. + * + * Regarding the CLK_IGNORE_UNUSED flag: + * Clocks flagged CLK_IGNORE_UNUSED are not consumed by any driver. The flag + * keeps them in their hardware default state (enabled) instead of letting + * the clock framework gate them once it disables unused clocks. If this + * flag needs to be removed later, it must be ensured that these clocks will + * not be disabled even if they are not consumed. + */ +static const struct jh71x0_clk_data jhb100_per1crg_clk_data[] = { + JH71X0__DIV(JHB100_PER1CLK_100, "per1_100", 8, JHB100_PER1CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER1CLK_1, "per1_1", 100, JHB100_PER1CLK_100), + JH71X0__DIV(JHB100_PER1CLK_200_DIVN0, "200_divn0", 256, + JHB100_PER1CLK_CFG_800), + JH71X0__DIV(JHB100_PER1CLK_200_DIVN1, "200_divn1", 256, + JHB100_PER1CLK_CFG_800), + JH71X0__DIV(JHB100_PER1CLK_200_DIVN2, "200_divn2", 256, + JHB100_PER1CLK_CFG_800), + JH71X0__DIV(JHB100_PER1CLK_200_DIVN3, "200_divn3", 256, + JHB100_PER1CLK_CFG_800), + JH71X0__DIV(JHB100_PER1CLK_200_CCLK_DIV, "200_cclk_div", 2046, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_SGPIO0_PCLK, "sgpio0_pclk", CLK_IGNORE_UNUSED, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_SGPIO0_DCLK, "sgpio0_dclk", 0, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_SGPIO1_PCLK, "sgpio1_pclk", CLK_IGNORE_UNUSED, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_SGPIO1_DCLK, "sgpio1_dclk", 0, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_EMMC0_BCLK, "emmc0_bclk", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_EMMC0_CCLK, "emmc0_cclk", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC1_1CH_CORE, "dmac1_1ch_core", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC1_1CH_ACLK, "dmac1_1ch_aclk", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC2_1CH_CORE, "dmac2_1ch_core", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC2_1CH_ACLK, "dmac2_1ch_aclk", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC3_1CH_CORE, "dmac3_1ch_core", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC3_1CH_ACLK, "dmac3_1ch_aclk", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC0_2CH_CORE, "dmac0_2ch_core", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_DMAC0_2CH_ACLK, "dmac0_2ch_aclk", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0__DIV(JHB100_PER1CLK_UFS_REF, "ufs_ref", 75, + JHB100_PER1CLK_PLL7), + JH71X0__DIV(JHB100_PER1CLK_UFS_300, "ufs_300", 2, + JHB100_PER1CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER1CLK_UFS_150, "ufs_150", 12, + JHB100_PER1CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER1CLK_UFS_400, "ufs_400", 2, + JHB100_PER1CLK_CFG_800), + JH71X0__DIV(JHB100_PER1CLK_UFS_75, "ufs_75", 2, + JHB100_PER1CLK_UFS_150), + JH71X0__DIV(JHB100_PER1CLK_UFS_37_5, "ufs_37_5", 2, + JHB100_PER1CLK_UFS_75), + JH71X0__DIV(JHB100_PER1CLK_UFS_7_5, "ufs_7_5", 10, + JHB100_PER1CLK_UFS_75), + JH71X0__DIV(JHB100_PER1CLK_UFS_1_875, "ufs_1_875", 4, + JHB100_PER1CLK_UFS_7_5), + JH71X0__DIV(JHB100_PER1CLK_UFS_7_143, "ufs_7_143", 20, + JHB100_PER1CLK_CFG_143), + JH71X0__DIV(JHB100_PER1CLK_UFS_3_5715, "ufs_3_5715", 2, + JHB100_PER1CLK_UFS_7_143), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC0, "main_icg_en_sfc0", CLK_IS_CRITICAL, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC1, "main_icg_en_sfc1", CLK_IS_CRITICAL, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SFC2, "main_icg_en_sfc2", CLK_IS_CRITICAL, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SPI0, "main_icg_en_spi0", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_EMMC0, "main_icg_en_emmc0", 0, + JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SGPIO0, "main_icg_en_sgpio0", 0, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SGPIO1, "main_icg_en_sgpio1", 0, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_SENSORS_PERIPH1, "main_icg_en_sensors_periph1", 0, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC0, "main_icg_en_dmac_sfc0", + CLK_IS_CRITICAL, JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC1, "main_icg_en_dmac_sfc1", + CLK_IS_CRITICAL, JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC2, "main_icg_en_dmac_sfc2", + CLK_IS_CRITICAL, JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SPI0, "main_icg_en_dmac_spi0", + CLK_IS_CRITICAL, JHB100_PER1CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_RAS, "main_icg_en_ras", 0, + JHB100_PER1CLK_100), + JH71X0_GATE(JHB100_PER1CLK_MAIN_ICG_EN_UFS, "main_icg_en_ufs", 0, + JHB100_PER1CLK_100), +}; + +static const struct jh71x0_crg_domain_info jhb100_per1crg_info = { + .clk_data = jhb100_per1crg_clk_data, + .num_clk = ARRAY_SIZE(jhb100_per1crg_clk_data), + .ext_clk = jhb100_per1_ext_clk, + .num_ext_clk = ARRAY_SIZE(jhb100_per1_ext_clk), + .rst_name = "jhb100-r-per1", + .power_domain = false, +}; + +static const struct of_device_id jhb100_per1crg_match[] = { + { + .compatible = "starfive,jhb100-per1crg", + .data = &jhb100_per1crg_info, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_per1crg_driver = { + .probe = jh71x0_crg_probe, + .driver = { + .name = "clk-starfive-jhb100-per1", + .of_match_table = jhb100_per1crg_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(jhb100_per1crg_driver); -- 2.25.1