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Thu, 8 Oct 2026 12:34:02 +0000 From: Changhuang Liang To: Brian Masney , Jerome Brunet , Stephen Boyd , Philipp Zabel , Emil Renner Berthing Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Hal Feng , Changhuang Liang Subject: [PATCH v6 12/15] clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver Date: Thu, 8 Oct 2026 05:33:35 -0700 Message-Id: <20261008123338.11081-13-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261008123338.11081-1-changhuang.liang@starfivetech.com> References: <20261008123338.11081-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SHXPR01CA0017.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::26) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1268:EE_ X-MS-Office365-Filtering-Correlation-Id: 42e263ea-c953-4855-01a6-08df25386f35 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|7416014|1800799024|23010399003|366016|18002099003|22082099003|10067099003|56012099006|38350700014; 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Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 10 + drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-per2.c | 182 ++++++++++++++++++ 3 files changed, 193 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per2.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 62727ce3aef3..57a3838475e9 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -93,6 +93,16 @@ config CLK_STARFIVE_JHB100_PER1 Say yes here to support the peripheral-1 clock controller on the StarFive JHB100 SoC. +config CLK_STARFIVE_JHB100_PER2 + bool "StarFive JHB100 peripheral-2 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER + default ARCH_STARFIVE + help + Say yes here to support the peripheral-2 clock controller + on the StarFive JHB100 SoC. + config CLK_STARFIVE_JHB100_SYS0 bool "StarFive JHB100 system-0 clock support" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 279e0cdfc99b..ca9347d38023 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) += clk-starfive-jhb100-per2.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per2.c b/drivers/clk/starfive/clk-starfive-jhb100-per2.c new file mode 100644 index 000000000000..213f0fd9a260 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-per2.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 Peripheral-2 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include + +#include "clk-starfive-jh71x0.h" + +#define JHB100_PER2CLK_NUM_CLKS (JHB100_PER2CLK_MAIN_ICG_EN_GMAC3 + 1) + +/* external clocks */ +#define JHB100_PER2CLK_NCNOC_INIT (JHB100_PER2CLK_NUM_CLKS + 0) +#define JHB100_PER2CLK_CFG_400 (JHB100_PER2CLK_NUM_CLKS + 1) +#define JHB100_PER2CLK_CFG_125 (JHB100_PER2CLK_NUM_CLKS + 2) +#define JHB100_PER2CLK_GMAC2_RGMII_RX (JHB100_PER2CLK_NUM_CLKS + 3) +#define JHB100_PER2CLK_GMAC2_RMII_REF (JHB100_PER2CLK_NUM_CLKS + 4) +#define JHB100_PER2CLK_GMAC3_SGMII_TX (JHB100_PER2CLK_NUM_CLKS + 5) +#define JHB100_PER2CLK_GMAC3_SGMII_RX (JHB100_PER2CLK_NUM_CLKS + 6) +#define JHB100_PER2CLK_OSC (JHB100_PER2CLK_NUM_CLKS + 7) + +static const char * const jhb100_per2_ext_clk[] = { + "ncnoc_init", + "cfg_400", + "cfg_125", + "gmac2_rgmii_rx", + "gmac2_rmii_ref", + "gmac3_sgmii_tx", + "gmac3_sgmii_rx", + "osc", +}; + +/* + * Regarding the CLK_IGNORE_UNUSED flag: + * Clocks flagged CLK_IGNORE_UNUSED are not consumed by any driver. The flag + * keeps them in their hardware default state (enabled) instead of letting + * the clock framework gate them once it disables unused clocks. If this + * flag needs to be removed later, it must be ensured that these clocks will + * not be disabled even if they are not consumed. + */ +static const struct jh71x0_clk_data jhb100_per2crg_clk_data[] = { + JH71X0__DIV(JHB100_PER2CLK_300, "per2_300", 2, + JHB100_PER2CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER2CLK_100, "per2_100", 4, + JHB100_PER2CLK_CFG_400), + JH71X0__DIV(JHB100_PER2CLK_50, "per2_50", 2, + JHB100_PER2CLK_100), + JH71X0__DIV(JHB100_PER2CLK_GMAC2_RMII_50, "gmac2_rmii_50", 2, + JHB100_PER2CLK_100), + JH71X0__DIV(JHB100_PER2CLK_CAN0_CORE_DIV, "can0_core_div", 20, + JHB100_PER2CLK_CFG_400), + JH71X0__DIV(JHB100_PER2CLK_CAN1_CORE_DIV, "can1_core_div", 20, + JHB100_PER2CLK_CFG_400), + JH71X0__DIV(JHB100_PER2CLK_CAN0_TIMER, "can0_timer", 100, + JHB100_PER2CLK_100), + JH71X0__DIV(JHB100_PER2CLK_CAN1_TIMER, "can1_timer", 100, + JHB100_PER2CLK_100), + JH71X0__DIV(JHB100_PER2CLK_RTC_CORE_DIV, "rtc_core_div", 763, + JHB100_PER2CLK_OSC), + JH71X0__MUX(JHB100_PER2CLK_GMAC2_RMII_MUX_DLY, "gmac2_rmii_mux_dly", 0, 2, + JHB100_PER2CLK_GMAC2_RMII_REF, + JHB100_PER2CLK_GMAC2_RMII_50), + JH71X0__DIV(JHB100_PER2CLK_GMAC2_RMII_DIV, "gmac2_rmii_div", 20, + JHB100_PER2CLK_GMAC2_RMII_MUX_DLY), + JH71X0__MUX(JHB100_PER2CLK_GMAC2_RGMII_125_MUX, "gmac2_rgmii_125_mux", 0, 2, + JHB100_PER2CLK_GMAC2_RGMII_RX, + JHB100_PER2CLK_CFG_125), + JH71X0__DIV(JHB100_PER2CLK_GMAC2_RGMII_DIV, "gmac2_rgmii_div", 50, + JHB100_PER2CLK_CFG_125), + JH71X0__MUX(JHB100_PER2CLK_GMAC2_TX_MUX, "gmac2_tx_mux", 0, 2, + JHB100_PER2CLK_GMAC2_RMII_DIV, + JHB100_PER2CLK_GMAC2_RGMII_DIV), + JH71X0__INV(JHB100_PER2CLK_GMAC2_TX_180_BUF, "gmac2_tx_180_buf", + JHB100_PER2CLK_GMAC2_TX_MUX), + JH71X0__MUX(JHB100_PER2CLK_GMAC2_RX_MUX_DLY, "gmac2_rx_mux_dly", 0, 2, + JHB100_PER2CLK_GMAC2_RMII_DIV, + JHB100_PER2CLK_GMAC2_RGMII_125_MUX), + JH71X0__INV(JHB100_PER2CLK_GMAC2_RX_180_BUF, "gmac2_rx_180_buf", + JHB100_PER2CLK_GMAC2_RX_MUX_DLY), + JH71X0__MUX(JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY, "gmac2_txck_mux_dly", 0, 2, + JHB100_PER2CLK_GMAC2_RMII_50, + JHB100_PER2CLK_GMAC2_TX_MUX), + JH71X0__MUX(JHB100_PER2CLK_GMAC3_TX_125_MUX, "gmac3_tx_125_mux", 0, 2, + JHB100_PER2CLK_GMAC3_SGMII_TX, + JHB100_PER2CLK_CFG_125), + JH71X0__MUX(JHB100_PER2CLK_GMAC3_RX_125_MUX, "gmac3_rx_125_mux", 0, 2, + JHB100_PER2CLK_GMAC3_SGMII_RX, + JHB100_PER2CLK_CFG_125), + JH71X0__DIV(JHB100_PER2CLK_GMAC3_TX_DIV, "gmac3_tx_div", 50, + JHB100_PER2CLK_GMAC3_TX_125_MUX), + JH71X0__DIV(JHB100_PER2CLK_GMAC3_RX_DIV, "gmac3_rx_div", 50, + JHB100_PER2CLK_GMAC3_RX_125_MUX), + JH71X0_GATE(JHB100_PER2CLK_SENSORS_PERIPH2, "sensors_periph2", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_FAN_TACH_PCLK, "fan_tach_pclk", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_I, "ether0_rmiiandrgmii_tx_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_TX_MUX), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_I, "ether0_rmiiandrgmii_rx_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RX_MUX_DLY), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_180_I, "ether0_rmiiandrgmii_tx_180_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_TX_180_BUF), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_180_I, "ether0_rmiiandrgmii_rx_180_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RX_180_BUF), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_PTP_REF_I, "ether0_rmiiandrgmii_ptp_ref_i", + 0, JHB100_PER2CLK_50), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RMII_I, "ether0_rmiiandrgmii_rmii_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RMII_MUX_DLY), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_CSR_I, "ether0_rmiiandrgmii_csr_i", + 0, JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_ACLK_I, "ether0_rmiiandrgmii_aclk_i", + 0, JHB100_PER2CLK_300), + JH71X0_GATE(JHB100_PER2CLK_RMIIANDRGMII_IOMUX_GMAC2_TXCK, "rmiiandrgmii_iomux_gmac2_txck", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_TX_I, "ether1_sgmii_tx_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_TX_DIV), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_RX_I, "ether1_sgmii_rx_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_RX_DIV), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_TX_125_I, "ether1_sgmii_tx_125_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_TX_125_MUX), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_RX_125_I, "ether1_sgmii_rx_125_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_RX_125_MUX), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_PTP_REF_I, "ether1_sgmii_ptp_ref_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_50), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_CSR_I, "ether1_sgmii_csr_i", + 0, JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_ACLK_I, "ether1_sgmii_aclk_i", + 0, JHB100_PER2CLK_300), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_PHY_PCLK_I, "ether1_sgmii_phy_pclk_i", + 0, JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_ETHER1_SGMII_REF_25_I, "ether1_sgmii_ref_25_i", + CLK_IGNORE_UNUSED, JHB100_PER2CLK_OSC), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_CAN0, "main_icg_en_can0", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_CAN1, "main_icg_en_can1", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_DMAC_8CH, "main_icg_en_dmac_8ch", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_RTC_SCAN, "main_icg_en_rtc_scan", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_ADC0, "main_icg_en_adc0", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_ADC1, "main_icg_en_adc1", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_GMAC2, "main_icg_en_gmac2", 0, + JHB100_PER2CLK_100), + JH71X0_GATE(JHB100_PER2CLK_MAIN_ICG_EN_GMAC3, "main_icg_en_gmac3", 0, + JHB100_PER2CLK_100), +}; + +static const struct jh71x0_crg_domain_info jhb100_per2crg_info = { + .clk_data = jhb100_per2crg_clk_data, + .num_clk = ARRAY_SIZE(jhb100_per2crg_clk_data), + .ext_clk = jhb100_per2_ext_clk, + .num_ext_clk = ARRAY_SIZE(jhb100_per2_ext_clk), + .rst_name = "jhb100-r-per2", + .power_domain = false, +}; + +static const struct of_device_id jhb100_per2crg_match[] = { + { + .compatible = "starfive,jhb100-per2crg", + .data = &jhb100_per2crg_info, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_per2crg_driver = { + .probe = jh71x0_crg_probe, + .driver = { + .name = "clk-starfive-jhb100-per2", + .of_match_table = jhb100_per2crg_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(jhb100_per2crg_driver); -- 2.25.1