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Thu, 8 Oct 2026 12:34:03 +0000 From: Changhuang Liang To: Brian Masney , Jerome Brunet , Stephen Boyd , Philipp Zabel , Emil Renner Berthing Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Hal Feng , Changhuang Liang Subject: [PATCH v6 13/15] clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver Date: Thu, 8 Oct 2026 05:33:36 -0700 Message-Id: <20261008123338.11081-14-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261008123338.11081-1-changhuang.liang@starfivetech.com> References: <20261008123338.11081-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SHXPR01CA0017.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::26) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1268:EE_ X-MS-Office365-Filtering-Correlation-Id: a5f4c574-97a7-4710-8950-08df25386fdc X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|7416014|1800799024|23010399003|366016|18002099003|22082099003|10067099003|56012099006|38350700014; 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Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 10 ++ drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-per3.c | 140 ++++++++++++++++++ 3 files changed, 151 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per3.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 57a3838475e9..1c9dd5d47cb8 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -103,6 +103,16 @@ config CLK_STARFIVE_JHB100_PER2 Say yes here to support the peripheral-2 clock controller on the StarFive JHB100 SoC. +config CLK_STARFIVE_JHB100_PER3 + bool "StarFive JHB100 peripheral-3 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER + default ARCH_STARFIVE + help + Say yes here to support the peripheral-3 clock controller + on the StarFive JHB100 SoC. + config CLK_STARFIVE_JHB100_SYS0 bool "StarFive JHB100 system-0 clock support" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index ca9347d38023..2c4554c2e70e 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) += clk-starfive-jhb100-per2.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_PER3) += clk-starfive-jhb100-per3.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per3.c b/drivers/clk/starfive/clk-starfive-jhb100-per3.c new file mode 100644 index 000000000000..aa023a74ad72 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-per3.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 Peripheral-3 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include + +#include "clk-starfive-jh71x0.h" + +#define JHB100_PER3CLK_NUM_CLKS (JHB100_PER3CLK_MAIN_ICG_EN_GMAC1 + 1) + +/* external clocks */ +#define JHB100_PER3CLK_NCNOC_INIT (JHB100_PER3CLK_NUM_CLKS + 0) +#define JHB100_PER3CLK_NCNOC_TARG (JHB100_PER3CLK_NUM_CLKS + 1) +#define JHB100_PER3CLK_CFG_125 (JHB100_PER3CLK_NUM_CLKS + 2) +#define JHB100_PER3CLK_GMAC0_RMII_RCLKI (JHB100_PER3CLK_NUM_CLKS + 3) +#define JHB100_PER3CLK_GMAC1_SGMII_TX (JHB100_PER3CLK_NUM_CLKS + 4) +#define JHB100_PER3CLK_GMAC1_SGMII_RX (JHB100_PER3CLK_NUM_CLKS + 5) +#define JHB100_PER3CLK_OSC (JHB100_PER3CLK_NUM_CLKS + 6) + +static const char * const jhb100_per3_ext_clk[] = { + "ncnoc_init", + "ncnoc_targ", + "cfg_125", + "gmac0_rmii_rclki", + "gmac1_sgmii_tx", + "gmac1_sgmii_rx", + "osc", +}; + +/* + * Regarding the CLK_IGNORE_UNUSED flag: + * Clocks flagged CLK_IGNORE_UNUSED are not consumed by any driver. The flag + * keeps them in their hardware default state (enabled) instead of letting + * the clock framework gate them once it disables unused clocks. If this + * flag needs to be removed later, it must be ensured that these clocks will + * not be disabled even if they are not consumed. + */ +static const struct jh71x0_clk_data jhb100_per3crg_clk_data[] = { + JH71X0__DIV(JHB100_PER3CLK_300, "per3_300", 256, + JHB100_PER3CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER3CLK_200, "per3_200", 256, + JHB100_PER3CLK_NCNOC_INIT), + JH71X0__DIV(JHB100_PER3CLK_GMAC1_PTP_REF, "gmac1_ptp_ref", 2, + JHB100_PER3CLK_NCNOC_TARG), + JH71X0__MUX(JHB100_PER3CLK_GMAC1_TX_125_MUX, "gmac1_tx_125_mux", 0, 2, + JHB100_PER3CLK_GMAC1_SGMII_TX, + JHB100_PER3CLK_CFG_125), + JH71X0__DIV(JHB100_PER3CLK_GMAC1_TX, "gmac1_tx", 50, + JHB100_PER3CLK_GMAC1_TX_125_MUX), + JH71X0__MUX(JHB100_PER3CLK_GMAC1_RX_125_MUX, "gmac1_rx_125_mux", 0, 2, + JHB100_PER3CLK_GMAC1_SGMII_RX, + JHB100_PER3CLK_CFG_125), + JH71X0__DIV(JHB100_PER3CLK_GMAC1_RX, "gmac1_rx", 50, + JHB100_PER3CLK_GMAC1_RX_125_MUX), + JH71X0__DIV(JHB100_PER3CLK_GMAC0_PTP_REF, "gmac0_ptp_ref", 2, + JHB100_PER3CLK_NCNOC_TARG), + JH71X0__DIV(JHB100_PER3CLK_GMAC0_RMII_PLL, "gmac0_rmii_pll", 2, + JHB100_PER3CLK_NCNOC_TARG), + JH71X0__MUX(JHB100_PER3CLK_GMAC0_RMII_MUX, "gmac0_rmii_mux", 0, 2, + JHB100_PER3CLK_GMAC0_RMII_PLL, + JHB100_PER3CLK_GMAC0_RMII_RCLKI), + JH71X0__DIV(JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2, "gmac0_rmii_mux_div2", 20, + JHB100_PER3CLK_GMAC0_RMII_MUX), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_TX_I, "ether0_rmii_clk_tx_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_RX_I, "ether0_rmii_clk_rx_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_PTP_REF_I, "ether0_rmii_clk_ptp_ref_i", + 0, JHB100_PER3CLK_GMAC0_PTP_REF), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_RMII_I, "ether0_rmii_clk_rmii_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_CSR_I, "ether0_rmii_clk_csr_i", + 0, JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_RMII_ACLK_I, "ether0_rmii_aclk_i", + 0, JHB100_PER3CLK_300), + JH71X0_GATE(JHB100_PER3CLK_GMAC0_RMII_RCLKO, "gmac0_rmii_rclko", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_PLL), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_I, "ether0_sgmii_clk_tx_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_TX), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_I, "ether0_sgmii_clk_rx_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_RX), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_125_I, "ether0_sgmii_clk_tx_125_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_TX_125_MUX), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_125_I, "ether0_sgmii_clk_rx_125_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_RX_125_MUX), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_PTP_REF_I, "ether0_sgmii_clk_ptp_ref_i", + 0, JHB100_PER3CLK_GMAC1_PTP_REF), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_REF_25_I, "ether0_sgmii_clk_ref_25_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_OSC), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_CSR_I, "ether0_sgmii_clk_csr_i", + 0, JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_ACLK_I, "ether0_sgmii_aclk_i", + 0, JHB100_PER3CLK_300), + JH71X0_GATE(JHB100_PER3CLK_ETHER0_SGMII_PHY_PCLK_I, "ether0_sgmii_phy_pclk_i", + CLK_IGNORE_UNUSED, JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_MAIN_ICG_EN_SENSORS_PERIPH3, "main_icg_en_sensors_periph3", 0, + JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_MAIN_ICG_EN_PECI0, "main_icg_en_peci0", 0, + JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_MAIN_ICG_EN_PECI1, "main_icg_en_peci1", 0, + JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_MAIN_ICG_EN_GMAC0, "main_icg_en_gmac0", + 0, JHB100_PER3CLK_NCNOC_TARG), + JH71X0_GATE(JHB100_PER3CLK_MAIN_ICG_EN_GMAC1, "main_icg_en_gmac1", + 0, JHB100_PER3CLK_NCNOC_TARG), +}; + +static const struct jh71x0_crg_domain_info jhb100_per3crg_info = { + .clk_data = jhb100_per3crg_clk_data, + .num_clk = ARRAY_SIZE(jhb100_per3crg_clk_data), + .ext_clk = jhb100_per3_ext_clk, + .num_ext_clk = ARRAY_SIZE(jhb100_per3_ext_clk), + .rst_name = "jhb100-r-per3", + .power_domain = false, +}; + +static const struct of_device_id jhb100_per3crg_match[] = { + { + .compatible = "starfive,jhb100-per3crg", + .data = &jhb100_per3crg_info, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_per3crg_driver = { + .probe = jh71x0_crg_probe, + .driver = { + .name = "clk-starfive-jhb100-per3", + .of_match_table = jhb100_per3crg_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(jhb100_per3crg_driver); -- 2.25.1