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Thu, 8 Oct 2026 12:33:53 +0000 From: Changhuang Liang To: Brian Masney , Jerome Brunet , Stephen Boyd , Philipp Zabel , Emil Renner Berthing Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Hal Feng , Changhuang Liang Subject: [PATCH v6 04/15] clk: starfive: jh71x0: Add generic CRG probe helper Date: Thu, 8 Oct 2026 05:33:27 -0700 Message-Id: <20261008123338.11081-5-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261008123338.11081-1-changhuang.liang@starfivetech.com> References: <20261008123338.11081-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SHXPR01CA0017.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::26) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1268:EE_ X-MS-Office365-Filtering-Correlation-Id: b9b5db67-3780-4e1f-fa35-08df253869b6 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|7416014|1800799024|23010399003|366016|18002099003|22082099003|10067099003|56012099006|38350700014; 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Add jh71x0_crg_probe() together with struct jh71x0_crg_domain_info so that each CRG driver only needs to provide its clock table, external clock names and reset auxiliary device name. The reset auxiliary device is registered with jh71x0_reset_controller_register(). The clock index space of these CRGs is sparse, so also make jh71x0_clk_get() reject indexes that were never registered when the domain info is available. Signed-off-by: Changhuang Liang --- drivers/clk/starfive/clk-starfive-jh71x0.c | 98 +++++++++++++++++++++- drivers/clk/starfive/clk-starfive-jh71x0.h | 12 +++ 2 files changed, 107 insertions(+), 3 deletions(-) diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c index 2cc71f49ddee..c5ee82db3c92 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.c +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include #include @@ -334,10 +336,14 @@ struct clk_hw *jh71x0_clk_get(struct of_phandle_args *clkspec, void *data) struct jh71x0_clk_priv *priv = data; unsigned int idx = clkspec->args[0]; - if (idx < priv->num_reg) - return &priv->reg[idx].hw; + if (idx >= priv->num_reg) + return ERR_PTR(-EINVAL); - return ERR_PTR(-EINVAL); + /* Index space is sparse: reject holes that were never registered. */ + if (priv->info && !priv->info->clk_data[idx].name) + return ERR_PTR(-ENOENT); + + return &priv->reg[idx].hw; } EXPORT_SYMBOL_GPL(jh71x0_clk_get); @@ -391,3 +397,89 @@ int jh71x0_reset_controller_register(struct jh71x0_clk_priv *priv, jh71x0_reset_unregister_adev, adev); } EXPORT_SYMBOL_GPL(jh71x0_reset_controller_register); + +int jh71x0_crg_probe(struct platform_device *pdev) +{ + const struct jh71x0_crg_domain_info *info; + struct jh71x0_clk_priv *priv; + unsigned int idx; + int ret; + + info = device_get_match_data(&pdev->dev); + if (!info) + return -ENODEV; + + priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, info->num_clk), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->rmw_lock); + priv->info = info; + priv->num_reg = info->num_clk; + priv->dev = &pdev->dev; + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + if (info->power_domain) { + ret = devm_pm_runtime_enable(priv->dev); + if (ret) + return dev_err_probe(priv->dev, ret, + "failed to enable runtime PM\n"); + } + + for (idx = 0; idx < info->num_clk; idx++) { + u32 max = info->clk_data[idx].max; + struct clk_parent_data parents[4] = {}; + struct clk_init_data init = { + .name = info->clk_data[idx].name, + .ops = starfive_jh71x0_clk_ops(max), + .parent_data = parents, + .num_parents = + ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + .flags = info->clk_data[idx].flags, + }; + struct jh71x0_clk *clk = &priv->reg[idx]; + unsigned int i; + + if (!init.name) + continue; + + if (init.num_parents > ARRAY_SIZE(parents)) + return dev_err_probe(priv->dev, -EINVAL, + "clock %s: too many parents (%u > %zu)\n", + init.name, init.num_parents, ARRAY_SIZE(parents)); + + for (i = 0; i < init.num_parents; i++) { + unsigned int pidx = info->clk_data[idx].parents[i]; + + if (pidx < info->num_clk) { + parents[i].hw = &priv->reg[pidx].hw; + } else { + if (pidx - info->num_clk >= info->num_ext_clk) + return dev_err_probe(priv->dev, -EINVAL, + "clock %s: invalid parent index %u\n", + init.name, pidx); + + parents[i].fw_name = info->ext_clk[pidx - info->num_clk]; + } + } + + clk->hw.init = &init; + clk->idx = idx; + clk->max_div = max & JH71X0_CLK_DIV_MASK; + + ret = devm_clk_hw_register(&pdev->dev, &clk->hw); + if (ret) + return dev_err_probe(priv->dev, ret, "Failed to register clock %s\n", + init.name); + } + + ret = devm_of_clk_add_hw_provider(&pdev->dev, jh71x0_clk_get, priv); + if (ret) + return ret; + + return jh71x0_reset_controller_register(priv, info->rst_name); +} +EXPORT_SYMBOL_GPL(jh71x0_crg_probe); diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h index 322a05157faf..2a1f0fb4cbb1 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.h +++ b/drivers/clk/starfive/clk-starfive-jh71x0.h @@ -5,6 +5,7 @@ #include #include #include +#include #include /* register fields */ @@ -109,6 +110,15 @@ struct jh71x0_clk { unsigned int max_div; }; +struct jh71x0_crg_domain_info { + const struct jh71x0_clk_data *clk_data; + unsigned int num_clk; + const char * const *ext_clk; + unsigned int num_ext_clk; + const char *rst_name; + bool power_domain; +}; + struct jh71x0_clk_priv { /* protect clk enable and set rate/parent from happening at the same time */ spinlock_t rmw_lock; @@ -116,6 +126,7 @@ struct jh71x0_clk_priv { void __iomem *base; struct clk *original_clk; struct notifier_block pll_clk_nb; + const struct jh71x0_crg_domain_info *info; struct clk_hw *pll[3]; unsigned int num_reg; struct jh71x0_clk reg[] __counted_by(num_reg); @@ -125,5 +136,6 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max); struct clk_hw *jh71x0_clk_get(struct of_phandle_args *clkspec, void *data); int jh71x0_reset_controller_register(struct jh71x0_clk_priv *priv, const char *adev_name); +int jh71x0_crg_probe(struct platform_device *pdev); #endif -- 2.25.1