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Thu, 8 Oct 2026 12:33:55 +0000 From: Changhuang Liang To: Brian Masney , Jerome Brunet , Stephen Boyd , Philipp Zabel , Emil Renner Berthing Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Hal Feng , Changhuang Liang Subject: [PATCH v6 06/15] clk: starfive: Add JHB100 System-1 clock generator driver Date: Thu, 8 Oct 2026 05:33:29 -0700 Message-Id: <20261008123338.11081-7-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261008123338.11081-1-changhuang.liang@starfivetech.com> References: <20261008123338.11081-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SHXPR01CA0017.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::26) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1268:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e124af6-810b-477e-4335-08df25386b0a X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|7416014|1800799024|23010399003|366016|18002099003|22082099003|10067099003|56012099006|38350700014; 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Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 10 ++ drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-sys1.c | 118 ++++++++++++++++++ 3 files changed, 129 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys1.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index cd5b7754403e..11da8bcc4046 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -82,3 +82,13 @@ config CLK_STARFIVE_JHB100_SYS0 help Say yes here to support the system-0 clock controller on the StarFive JHB100 SoC. + +config CLK_STARFIVE_JHB100_SYS1 + bool "StarFive JHB100 system-1 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER + default ARCH_STARFIVE + help + Say yes here to support the system-1 clock controller on the + StarFive JHB100 SoC. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index d2ba83d7d02c..0061550e0f7e 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys1.c b/drivers/clk/starfive/clk-starfive-jhb100-sys1.c new file mode 100644 index 000000000000..db37b243db18 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-sys1.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 System-1 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include +#include + +#include "clk-starfive-jh71x0.h" + +#define JHB100_SYS1CLK_NUM_CLKS (JHB100_SYS1CLK_BMCPER3_CFG_125 + 1) + +/* external clocks */ +#define JHB100_SYS1CLK_OSC (JHB100_SYS1CLK_NUM_CLKS + 0) +#define JHB100_SYS1CLK_PLL0 (JHB100_SYS1CLK_NUM_CLKS + 1) +#define JHB100_SYS1CLK_PLL1 (JHB100_SYS1CLK_NUM_CLKS + 2) +#define JHB100_SYS1CLK_PLL2 (JHB100_SYS1CLK_NUM_CLKS + 3) +#define JHB100_SYS1CLK_PLL4 (JHB100_SYS1CLK_NUM_CLKS + 4) +#define JHB100_SYS1CLK_PLL5 (JHB100_SYS1CLK_NUM_CLKS + 5) +#define JHB100_SYS1CLK_NPU_NCNOC_INIT (JHB100_SYS1CLK_NUM_CLKS + 6) + +static const char * const jhb100_sys1_ext_clk[] = { + "osc", + "pll0", + "pll1", + "pll2", + "pll4", + "pll5", + "npu_ncnoc_init", +}; + +/* + * Regarding the CLK_IS_CRITICAL flag: + * Clocks flagged CLK_IS_CRITICAL feed logic that has to keep running whether + * or not a consumer holds them, such as the bus interconnect and always-on + * blocks. Gating them hangs the system, so they must never be disabled. + * + * Regarding the CLK_IGNORE_UNUSED flag: + * Clocks flagged CLK_IGNORE_UNUSED are not consumed by any driver. The flag + * keeps them in their hardware default state (enabled) instead of letting + * the clock framework gate them once it disables unused clocks. If this + * flag needs to be removed later, it must be ensured that these clocks will + * not be disabled even if they are not consumed. + */ +static const struct jh71x0_clk_data jhb100_sys1crg_clk_data[] = { + /* root */ + JH71X0__DIV(JHB100_SYS1CLK_APB_MAIN_SYS1, "apb_main_sys1", 12, + JHB100_SYS1CLK_PLL1), + /* sensor */ + JH71X0_GATE(JHB100_SYS1CLK_APB_SENSOR_ICG_BUF, "apb_sensor_icg_buf", + CLK_IS_CRITICAL, JHB100_SYS1CLK_APB_MAIN_SYS1), + /* hostss1 */ + JH71X0__DIV(JHB100_SYS1CLK_GPIO_ESPI1_EXT, "gpio_espi1_ext", 14, + JHB100_SYS1CLK_PLL2), + JH71X0__DIV(JHB100_SYS1CLK_HOSTSS1_NCNOC_CFG, "hostss1_ncnoc_cfg", 12, + JHB100_SYS1CLK_PLL1), + JH71X0_GATE(JHB100_SYS1CLK_HOSTSS1_PHY_SCAN_1000_ICG_BUF, + "hostss1_phy_scan_1000_icg_buf", CLK_IS_CRITICAL, + JHB100_SYS1CLK_PLL1), + /* npu */ + JH71X0__DIV(JHB100_SYS1CLK_NPU_NCNOC_CFG, "npu_ncnoc_cfg", 6, + JHB100_SYS1CLK_PLL1), + JH71X0__DIV(JHB100_SYS1CLK_NPU_CORE_DIV, "npu_core_div", 10, + JHB100_SYS1CLK_PLL0), + JH71X0_GATE(JHB100_SYS1CLK_DOM_NPU_CORE_CLK, "dom_npu_core_clk", + CLK_IS_CRITICAL, JHB100_SYS1CLK_NPU_CORE_DIV), + JH71X0_GATE(JHB100_SYS1CLK_DOM_NPU_BUS_CLK, "dom_npu_bus_clk", + CLK_IS_CRITICAL, JHB100_SYS1CLK_NPU_NCNOC_INIT), + JH71X0_GATE(JHB100_SYS1CLK_DOM_NPU_INIT_CLK, "dom_npu_init_clk", + CLK_IS_CRITICAL, JHB100_SYS1CLK_NPU_NCNOC_CFG), + JH71X0_GATE(JHB100_SYS1CLK_DOM_NPU_OSC_CLK, "dom_npu_osc_clk", + CLK_IS_CRITICAL, JHB100_SYS1CLK_OSC), + /* vout */ + JH71X0__DIV(JHB100_SYS1CLK_VOUT_NCNOC_TARG, "vout_ncnoc_targ", 12, + JHB100_SYS1CLK_PLL1), + JH71X0__DIV(JHB100_SYS1CLK_VOUT_PIX0, "vout_pix0", 4, + JHB100_SYS1CLK_PLL4), + JH71X0__DIV(JHB100_SYS1CLK_VOUT_PIX1, "vout_pix1", 4, + JHB100_SYS1CLK_PLL5), + /* bmcperiph3 */ + JH71X0__DIV(JHB100_SYS1CLK_BMCPER3_NCNOC_TARG, "bmcper3_ncnoc_targ", 12, + JHB100_SYS1CLK_PLL1), + JH71X0__DIV(JHB100_SYS1CLK_BMCPER3_CFG_125, "bmcper3_cfg_125", 10, + JHB100_SYS1CLK_PLL1), +}; + +static const struct jh71x0_crg_domain_info jhb100_sys1crg_info = { + .clk_data = jhb100_sys1crg_clk_data, + .num_clk = ARRAY_SIZE(jhb100_sys1crg_clk_data), + .ext_clk = jhb100_sys1_ext_clk, + .num_ext_clk = ARRAY_SIZE(jhb100_sys1_ext_clk), + .rst_name = "jhb100-r-sys1", + .power_domain = false, +}; + +static const struct of_device_id jhb100_sys1crg_match[] = { + { + .compatible = "starfive,jhb100-sys1crg", + .data = &jhb100_sys1crg_info, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_sys1crg_driver = { + .probe = jh71x0_crg_probe, + .driver = { + .name = "clk-starfive-jhb100-sys1", + .of_match_table = jhb100_sys1crg_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(jhb100_sys1crg_driver); -- 2.25.1