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Thu, 8 Oct 2026 12:33:56 +0000 From: Changhuang Liang To: Brian Masney , Jerome Brunet , Stephen Boyd , Philipp Zabel , Emil Renner Berthing Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Hal Feng , Changhuang Liang Subject: [PATCH v6 07/15] clk: starfive: Add JHB100 System-2 clock generator driver Date: Thu, 8 Oct 2026 05:33:30 -0700 Message-Id: <20261008123338.11081-8-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261008123338.11081-1-changhuang.liang@starfivetech.com> References: <20261008123338.11081-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SHXPR01CA0017.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::26) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1268:EE_ X-MS-Office365-Filtering-Correlation-Id: 392c7c36-e984-43a6-ec7c-08df25386bb4 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|7416014|1800799024|23010399003|366016|18002099003|22082099003|10067099003|56012099006|38350700014; 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Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 10 ++ drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-sys2.c | 135 ++++++++++++++++++ 3 files changed, 146 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys2.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 11da8bcc4046..cfaac934a8e0 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -92,3 +92,13 @@ config CLK_STARFIVE_JHB100_SYS1 help Say yes here to support the system-1 clock controller on the StarFive JHB100 SoC. + +config CLK_STARFIVE_JHB100_SYS2 + bool "StarFive JHB100 system-2 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER + default ARCH_STARFIVE + help + Say yes here to support the system-2 clock controller on the + StarFive JHB100 SoC. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 0061550e0f7e..29cdef20575e 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys2.c b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c new file mode 100644 index 000000000000..405f45a3042a --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 System-2 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include +#include + +#include "clk-starfive-jh71x0.h" + +#define JHB100_SYS2CLK_NUM_CLKS (JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 + 1) + +/* external clocks */ +#define JHB100_SYS2CLK_OSC (JHB100_SYS2CLK_NUM_CLKS + 0) +#define JHB100_SYS2CLK_PLL1 (JHB100_SYS2CLK_NUM_CLKS + 1) +#define JHB100_SYS2CLK_GPU0_NCNOC_INIT (JHB100_SYS2CLK_NUM_CLKS + 2) +#define JHB100_SYS2CLK_GPU1_NCNOC_INIT (JHB100_SYS2CLK_NUM_CLKS + 3) + +static const char * const jhb100_sys2_ext_clk[] = { + "osc", + "pll1", + "gpu0_ncnoc_init", + "gpu1_ncnoc_init", +}; + +/* + * Regarding the CLK_IS_CRITICAL flag: + * Clocks flagged CLK_IS_CRITICAL feed logic that has to keep running whether + * or not a consumer holds them, such as the bus interconnect and always-on + * blocks. Gating them hangs the system, so they must never be disabled. + */ +static const struct jh71x0_clk_data jhb100_sys2crg_clk_data[] = { + /* jtag mst*/ + JH71X0__DIV(JHB100_SYS2CLK_JTAGM0_HCLK, "jtagm0_hclk", 6, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_JTAGM1_HCLK, "jtagm1_hclk", 6, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_JTAGM0_ATPG, "jtagm0_atpg", 12, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_JTAGM1_ATPG, "jtagm1_atpg", 12, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_JTAGM0_ATPG_TCLOCK, "jtagm0_atpg_tclock", 2, + JHB100_SYS2CLK_JTAGM0_ATPG), + JH71X0__DIV(JHB100_SYS2CLK_JTAGM1_ATPG_TCLOCK, "jtagm1_atpg_tclock", 2, + JHB100_SYS2CLK_JTAGM1_ATPG), + JH71X0_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_HCLK, "jtag0_mst_wrap_hclk", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_HCLK), + JH71X0_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_CLK_JTAG, "jtag0_mst_wrap_clk_jtag", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_HCLK), + JH71X0_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_APB_PCLK, "jtag0_mst_wrap_apb_pclk", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_ATPG), + JH71X0_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_ATPG_TCLOCK, "jtag0_mst_wrap_atpg_tclock", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_ATPG), + JH71X0_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_HCLK, "jtag1_mst_wrap_hclk", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_HCLK), + JH71X0_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_CLK_JTAG, "jtag1_mst_wrap_clk_jtag", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_HCLK), + JH71X0_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_APB_PCLK, "jtag1_mst_wrap_apb_pclk", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_ATPG), + JH71X0_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_ATPG_TCLOCK, "jtag1_mst_wrap_atpg_tclock", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_ATPG), + /* hostusbcmn */ + JH71X0__DIV(JHB100_SYS2CLK_HOSTUSB_NCNOC_TARG, "hostusb_ncnoc_targ", 12, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_HOSTUSBCMN_CFG_500, "hostusbcmn_cfg_500", 4, + JHB100_SYS2CLK_PLL1), + /* bmcperiph1 */ + JH71X0__DIV(JHB100_SYS2CLK_BMCPER1_NCNOC_TARG, "bmcper1_ncnoc_targ", 6, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_BMCPER1_CFG_250, "bmcper1_cfg_250", 5, + JHB100_SYS2CLK_PLL1), + JH71X0__DIV(JHB100_SYS2CLK_BMCPER1_CFG_143_DFT, "bmcper1_cfg_143_dft", 8, + JHB100_SYS2CLK_PLL1), + JH71X0_GATE(JHB100_SYS2CLK_BMCPER1_CFG_143, "bmcper1_cfg_143", CLK_IS_CRITICAL, + JHB100_SYS2CLK_BMCPER1_CFG_143_DFT), + /* bmcperiph0 */ + JH71X0__DIV(JHB100_SYS2CLK_BMCPER0_NCNOC_TARG, "bmcper0_ncnoc_targ", 6, + JHB100_SYS2CLK_PLL1), + /* gpu0 */ + JH71X0__DIV(JHB100_SYS2CLK_GPU0_NCNOC_TARG, "gpu0_ncnoc_targ", 12, + JHB100_SYS2CLK_PLL1), + JH71X0_GATE(JHB100_SYS2CLK_GPU0_BUS_CLK, "gpu0_bus_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_GPU0_NCNOC_INIT), + JH71X0_GATE(JHB100_SYS2CLK_GPU0_APB_CLK, "gpu0_apb_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_GPU0_NCNOC_TARG), + JH71X0_GATE(JHB100_SYS2CLK_GPU0_OSC_CLK, "gpu0_osc_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_OSC), + /* gpu1 */ + JH71X0__DIV(JHB100_SYS2CLK_GPU1_NCNOC_TARG, "gpu1_ncnoc_targ", 12, + JHB100_SYS2CLK_PLL1), + JH71X0_GATE(JHB100_SYS2CLK_GPU1_BUS_CLK, "gpu1_bus_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_GPU1_NCNOC_INIT), + JH71X0_GATE(JHB100_SYS2CLK_GPU1_APB_CLK, "gpu1_apb_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_GPU1_NCNOC_TARG), + JH71X0_GATE(JHB100_SYS2CLK_GPU1_OSC_CLK, "gpu1_osc_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_OSC), + /* main icg */ + JH71X0_GATE(JHB100_SYS2CLK_MAIN_ICG_EN_JTAG0, "main_icg_en_jtag0", 0, + JHB100_SYS2CLK_JTAGM0_HCLK), + JH71X0_GATE(JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1, "main_icg_en_jtag1", 0, + JHB100_SYS2CLK_JTAGM1_HCLK), +}; + +static const struct jh71x0_crg_domain_info jhb100_sys2crg_info = { + .clk_data = jhb100_sys2crg_clk_data, + .num_clk = ARRAY_SIZE(jhb100_sys2crg_clk_data), + .ext_clk = jhb100_sys2_ext_clk, + .num_ext_clk = ARRAY_SIZE(jhb100_sys2_ext_clk), + .rst_name = "jhb100-r-sys2", + .power_domain = false, +}; + +static const struct of_device_id jhb100_sys2crg_match[] = { + { + .compatible = "starfive,jhb100-sys2crg", + .data = &jhb100_sys2crg_info, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_sys2crg_driver = { + .probe = jh71x0_crg_probe, + .driver = { + .name = "clk-starfive-jhb100-sys2", + .of_match_table = jhb100_sys2crg_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(jhb100_sys2crg_driver); -- 2.25.1