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[34.147.45.103]) by smtp.gmail.com with UTF8SMTPSA id 4fb4d7f45d1cf-6b00a921c67sm1407491a12.21.2026.10.08.06.41.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Oct 2026 06:41:07 -0700 (PDT) From: Andrei Kuchynski To: Jameson Thies , Benson Leung , Abhishek Pandit-Subedi , Tzung-Bi Shih , Guenter Roeck Cc: chrome-platform@lists.linux.dev, linux-kernel@vger.kernel.org, Andrei Kuchynski Subject: [PATCH v2 2/2] platform/chrome: cros_ec_typec: Reorder altmode registration Date: Thu, 8 Oct 2026 13:40:56 +0000 Message-ID: <20261008134056.3816556-3-akuchynski@chromium.org> X-Mailer: git-send-email 2.56.0.360.g66cac248cb-goog In-Reply-To: <20261008134056.3816556-1-akuchynski@chromium.org> References: <20261008134056.3816556-1-akuchynski@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit By default, alternate mode priorities are set in registration order, with the last mode registered taking precedence. Changing the registration order of alternate modes prioritizes DisplayPort over Thunderbolt. Signed-off-by: Andrei Kuchynski --- drivers/platform/chrome/cros_ec_typec.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c index 718d06fa24132..b1bcf2ffb4176 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -406,17 +406,6 @@ static int cros_typec_register_port_altmodes(struct cros_typec_data *typec, struct typec_altmode_desc desc; struct typec_altmode *amode; - /* All PD capable CrOS devices are assumed to support DP altmode. */ - memset(&desc, 0, sizeof(desc)); - desc.svid = USB_TYPEC_DP_SID; - desc.mode = USB_TYPEC_DP_MODE; - desc.vdo = DP_PORT_VDO; - amode = cros_typec_register_displayport(port, &desc, - typec->ap_driven_altmode); - if (IS_ERR(amode)) - return PTR_ERR(amode); - port->port_altmode[CROS_EC_ALTMODE_DP] = amode; - /* * Register TBT compatibility alt mode. The EC will not enter the mode * if it doesn't support it and it will not enter automatically by @@ -433,6 +422,17 @@ static int cros_typec_register_port_altmodes(struct cros_typec_data *typec, port->port_altmode[CROS_EC_ALTMODE_TBT] = amode; } + /* All PD capable CrOS devices are assumed to support DP altmode. */ + memset(&desc, 0, sizeof(desc)); + desc.svid = USB_TYPEC_DP_SID; + desc.mode = USB_TYPEC_DP_MODE; + desc.vdo = DP_PORT_VDO; + amode = cros_typec_register_displayport(port, &desc, + typec->ap_driven_altmode); + if (IS_ERR(amode)) + return PTR_ERR(amode); + port->port_altmode[CROS_EC_ALTMODE_DP] = amode; + port->state.alt = NULL; port->state.mode = TYPEC_STATE_USB; port->state.data = NULL; -- 2.56.0.360.g66cac248cb-goog