From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B100D4399E5 for ; Thu, 8 Oct 2026 21:07:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791493653; cv=none; b=kY5eRkjfZstNwuDWmMa6WwSmbN3vEz9YQo3GRnumGYDPf1umCqOG64rlfBzCAlsf866s6VZGKHWOYOTJZhlQTLIITFvL6W2WddG8KiFT80EFvJJyGvEYr4fuGxDQ8HqK9W+Rk8hEc5rNx95B9Z1pt3OQc6rSj+g/RRiWvY+W+gM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791493653; c=relaxed/simple; bh=zsb3qQUwNEM19a5bOdye8GG/0Trdna7eKJrDi2YrJ6c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VH+y9D9FBL6oiM5DWfoq5StlBiDBmbC+VBwfCYAuEWuyVYLUICf2xFUg4kgbWTkjhihStRKIXM6uuDLyNe2bjZmrY2Pn3OuFlzLN55EUD/zgdrWiZGgrdZNlHRLU1z98Hmn1bXOSvH8/yxZ3CnV5AYQzElcsFq+BnWDWSMAHqqM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=WEw9wtfV; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=OzZ0xW8u; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="WEw9wtfV"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="OzZ0xW8u" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 698L04xk3648612 for ; Thu, 8 Oct 2026 21:07:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= yKtOOvFc5D27LCXFHoXF9QLWg5IasKf5P3xB+DwmaeQ=; b=WEw9wtfVjtcWxcyY 4VQo18+yoysdzuba7UA/qyi62cBJFbW4e8fSOPZEi/xpuazH6KX4iB5mtUiY5ZSi A/wmcBU/exDz6z1FY9ujCUD2cWXtTpfStyCZbOq3GSIx6XJ5lLVBIqsoEm6LxGdb tcvolzSUi5qkW+QoDyEyuRpJoJGoT+FAVehR+ffrgL4vHEDzDV4ncxW7+kJqUzs9 zHHtlsUqRADpOPWCoVWduf1UsIyh12RZx/zq7qwm/lwehCMXU179XKSUY9Qa2xNE Nra4w2om78oojEJCzmb7EgUN6W82SIzp7SPH4jRTFVZulDCDikklXCaepUyKBSCX 9dIjAA== Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h6fmqrqen-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 08 Oct 2026 21:07:30 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-3515d2fc5ebso9122780eec.1 for ; Thu, 08 Oct 2026 14:07:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1791493649; x=1792098449; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=yKtOOvFc5D27LCXFHoXF9QLWg5IasKf5P3xB+DwmaeQ=; b=OzZ0xW8uAr0702CIzsc9IHg6gpqM7azuep7sNsHvICMSmes7lTj2LrMbj9OleVQmj0 F56xQ5YlDjsQ+QLUo4vOxcgQMgX/+QO5CVhSP1SvQtOFaAChkH5m4At3M4k+3Ye3vYQG eiooK2+ObVeIgjndws9krh8fJeMIw7CKwxr8Y8rhDVIguUAmXvZ9rHN6SevcePB7868q S6apzGNb44YVNq0PO3/7hbl0L4zNYhcpvzadSC9D1Zz9a3qRAqVxe5L5qKQt17yQUuAG rT9bW+7UQ87R3Qv7KyGDZp0XqwNyNke0Ejc1hc462S1DHJtUg94qUfUJFpWxuWcun0jt qAag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1791493649; x=1792098449; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=yKtOOvFc5D27LCXFHoXF9QLWg5IasKf5P3xB+DwmaeQ=; b=uVKt5LZWRx2+uX1z3VlOHuUfUCSdg4ig9PXCU9T0ZykBrkO6Ff9utY9lq657KC3Fxp /QPywNkp0jkB8uOVabN4+ykaNVVxDS0zTFksfFFVjJww26XOuDCbQiUslfGQk5Gsm09I B3q6NwCBbPdnp4X2Z05rPbsz74ybrXzXWSSB7QXuSUKasVFySbOP/bd5K+8/orUALzBS WMa3o6SNoqOnalAN8LwKRqxO8ehEpfC3EOzoHnMSnZezFpqZkEdoeczeal5YY58XGqnp WmIO7D2X2VcDhpswukaLzGNYdZfeUqVpGPWdxtoMHpziIF3d2WJ8YitfJxz6Lh0XayI1 A+hw== X-Forwarded-Encrypted: i=1; AKwUvByJ25TYLxkk7Ox79p7Y22zHmEJDRYKOzqYP4QiY1UXxNl3I/By32hZ7C3kIah4Q0dUnA2hLTGabxw+HOEU=@vger.kernel.org X-Gm-Message-State: AFq9FYJzZPjQXMmulPg7bBS1TY8HEOW3oBbdmOCpCyrg+kMPvK1YTaah xmI3taFnGbOmj45GJUIJdpvG+nN3is7ET5pqUAjHU3icBsqDxconRtGLOtj2mGj3lhGpZISERnn xN+HmReseWBCDKFhUjUT4vt58EdoBBECv9rVSRiB6kHMo0qwnLeYmsrjJ5M+FNKRV5gE= X-Gm-Gg: AYBFou3XRnqEs6L5xNgRAXbdTJvmhR0y8eyhXAQGMJIU9hwtcKeXRQE100iPUbjHncv 1v/FXd73rVBhwbjzx3pWLXu2CnWTCpViTgzcheLjp3yfpWxfIWr6+ViRxKE1cDw6kpMRxkNIp75 UpGqQ2of53x5C9qFbudIX/RPsJvA0pWsP2zGB0rnHbnFnPyABfKx8mnGIfJQjmWm3cDD+7a4OkC S5IC3jNdvLexdR9OkUJAK7Wa2LGMnMU4qQSc4iQtx24uyXvqbu1+2MRVxD1ESWNMQNZ5h9DWut8 +x4JdOBFRUY7ULjSABiYtOGbPa4l3LXXVY1S0WqV+fyEIjIJqfFtqS0/Q09JF/KJyyWWTANV22q PVQwJCVWBzga5QzjVS96y+Aw= X-Received: by 2002:a05:693c:895a:10b0:343:9eb1:9940 with SMTP id 5a478bee46e88-3537e0270fbmr104202eec.26.1791493649296; Thu, 08 Oct 2026 14:07:29 -0700 (PDT) X-Received: by 2002:a05:693c:895a:10b0:343:9eb1:9940 with SMTP id 5a478bee46e88-3537e0270fbmr104146eec.26.1791493648753; Thu, 08 Oct 2026 14:07:28 -0700 (PDT) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3537cab27d5sm634773eec.17.2026.10.08.14.07.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Oct 2026 14:07:28 -0700 (PDT) From: Akhil P Oommen Date: Fri, 09 Oct 2026 02:36:37 +0530 Subject: [PATCH 3/5] arm64: dts: qcom: nord: Add Adreno 753 GPU and GMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261009-nord-gpu1-v1-3-a06a6c57bde7@oss.qualcomm.com> References: <20261009-nord-gpu1-v1-0-a06a6c57bde7@oss.qualcomm.com> In-Reply-To: <20261009-nord-gpu1-v1-0-a06a6c57bde7@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Akhil P Oommen , Shivam Rawat X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791493618; l=4289; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=6h4f7qVB4BKj8LihzL9H5wv7/el2Fm3tcb/8YO2NRo0=; b=g6Wbz6L+lGaMZuM2qLDwfWf242JVw9KWYgrDBLIggTh+WUYgs9DycTv52UscuMiOTt2a90FYP 4LEXEoArMpcCUOT6gk5uKG+7/ST2BxO4c0g3mq2are7+oqCK7P/a5tb X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA4MDA4NCBTYWx0ZWRfX42/OiCDhJtDY XsqSFLdIW6m+iX5uTXhef7oLtA/8S2hiuD6SvpnyV+Q9TRuXH/DiUZ997PugOVsqHCaho47zCwa GUiY4Ooz8B63036zAP5xPhG7r1QeIlM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA4MDA4NCBTYWx0ZWRfX74fyDRy9KHeb UAhfqTy2foVqsR4xhsb6X9NoaBob6sg8obEjeQa/kmJ3W5PfLTT0m8WoANHX3ffmQBIHpIaPRHU +xCu8A1g1Oh7g1heAoV0n85hQAfadE5Wulo2CvpKUCp0MMmTWpJ8NXSnz2IGjxCqr+MA+eXJwSR cx195V3OPC5ZRJmw6Jjv0Twv08D5Oqr9jqw9+Qh5TlnEhEoer2aIvCTsi3XMt07j/UlbkC+Jqon EHLMC6XvICJJbYGlvDmmU2hDBkvg1o/07lanpw2ls1m5ywIV5LQcZyXFW6VlK7o5EyKtScnWlEn X0bDXBm++6P18hps0KDI+r0mtR/tJA4fB+M1AkbC5+0uO5dW3zhAwqdDpyul9bkKqt0iiNswu/B C/ERUeTA9FbISz6wlK++ENHMmGqOZh6Auu3zj7TIJjsaXNKAe4NcK/B540f51OsQp4rnvQt7mYW EVyi1pFoyRx35kBNMwQ== X-Proofpoint-GUID: ULyDTKP2oH4snLO8hcgA7L9qGyClt6zY X-Proofpoint-ORIG-GUID: ULyDTKP2oH4snLO8hcgA7L9qGyClt6zY X-Authority-Analysis: v=2.4 cv=IqCL47/g c=1 sm=1 tr=0 ts=6ac80612 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=iMbq6FfIWUb5wk3_mucA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-08_07,2026-10-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 bulkscore=0 clxscore=1015 suspectscore=0 adultscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610080084 From: Shivam Rawat Nord SoC integrates an Adreno 753 GPU as its primary GPU, belonging to the A7xx Gen3 family, along with its Graphics Management Unit (GMU). Add the GPU and GMU nodes together with their OPP tables. The GPU sits behind adreno_smmu_0 and uses the gen71300 zap shader, while the GMU is clocked and powered from GPUCC. Unlike previous Adreno SoCs, where the GMU AXI clock comes from the single global clock controller, Nord splits its GCC into four blocks (GCC, SE_GCC, NE_GCC and NW_GCC). The GPU's AXI clock, NW_GCC_HSCNOC_GPU_AXI_CLK, is provided by NW_GCC, so the GMU node references nwgcc directly. Signed-off-by: Shivam Rawat Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 116 ++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi index 1ab7d9bc3cfe..4379092b7bf8 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -776,6 +776,122 @@ hscnoc: interconnect@2000000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + gpu_0: gpu@3d00000 { + compatible = "qcom,adreno-43051701", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x2000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu_0 0 0x0>, + <&adreno_smmu_0 1 0x0>; + + operating-points-v2 = <&gpu_opp_table_0>; + + qcom,gmu = <&gmu_0>; + #cooling-cells = <2>; + + interconnects = <&hscnoc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + status = "disabled"; + + gpu_0_zap_shader: zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + gpu_opp_table_0: opp-table { + compatible = "operating-points-v2-adreno", + "operating-points-v2"; + + opp-468000000 { + opp-hz = /bits/ 64 <468000000>; + opp-level = ; + opp-peak-kBps = <781250>; + }; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-level = ; + opp-peak-kBps = <6075000>; + }; + + opp-735000000 { + opp-hz = /bits/ 64 <735000000>; + opp-level = ; + opp-peak-kBps = <8175000>; + }; + + opp-854000000 { + opp-hz = /bits/ 64 <854000000>; + opp-level = ; + opp-peak-kBps = <10687500>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-level = ; + opp-peak-kBps = <12450000>; + }; + }; + }; + + gmu_0: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-753.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b2a0000 0x0 0x10000>; + reg-names = "gmu", + "rscc", + "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", + "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&nwgcc NW_GCC_HSCNOC_GPU_AXI_CLK>, + <&gpucc GPU_CC_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu_0 5 0x0>; + + operating-points-v2 = <&gmu_opp_table_0>; + + gmu_opp_table_0: opp-table { + compatible = "operating-points-v2"; + + opp-416666000 { + opp-hz = /bits/ 64 <416666000>; + opp-level = ; + }; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,nord-gpucc"; reg = <0x0 0x03d90000 0x0 0x9800>; -- 2.55.0