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Thu, 08 Oct 2026 19:01:11 -0700 (PDT) From: Jun Yan To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Liang Chen Cc: Jun Yan , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] arm64: dts: rockchip: Add dma-names to RK356x UART nodes Date: Fri, 9 Oct 2026 10:01:02 +0800 Message-ID: <20261009020103.364498-1-jerrysteve1101@gmail.com> X-Mailer: git-send-email 2.56.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The RK356x UART nodes define a dmas property but omit the matching dma-names property, so the 8250 driver fails to request a DMA channel and falls back to PIO, logging: of_dma_request_slave_channel: dma-names property of node '/serial@fe650000' missing or empty Add the missing dma-names = "tx", "rx" to uart0 through uart9, matching other Rockchip SoCs such as the RK3588. Fixes: a3adc0b9071d ("arm64: dts: rockchip: add core dtsi for RK3568 SoC") Signed-off-by: Jun Yan --- Changes in v2: - Add Fixes tag for the commit that introduced the dmas property. v1: https://lore.kernel.org/all/20261008153620.238580-1-jerrysteve1101@gmail.com/ arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index a5832895bd39..098493c04ecc 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -443,6 +443,7 @@ uart0: serial@fdd50000 { clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; pinctrl-0 = <&uart0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; @@ -1449,6 +1450,7 @@ uart1: serial@fe650000 { clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; pinctrl-0 = <&uart1m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; @@ -1463,6 +1465,7 @@ uart2: serial@fe660000 { clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 4>, <&dmac0 5>; + dma-names = "tx", "rx"; pinctrl-0 = <&uart2m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; @@ -1477,6 +1480,7 @@ uart3: serial@fe670000 { clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 6>, <&dmac0 7>; + dma-names = "tx", "rx"; pinctrl-0 = <&uart3m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; @@ -1491,6 +1495,7 @@ uart4: serial@fe680000 { clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 8>, <&dmac0 9>; + dma-names = "tx", "rx"; pinctrl-0 = <&uart4m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; @@ -1505,6 +1510,7 @@ uart5: serial@fe690000 { clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 10>, <&dmac0 11>; + dma-names = "tx", "rx"; pinctrl-0 = <&uart5m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; @@ -1519,6 +1525,7 @@ uart6: serial@fe6a0000 { clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 12>, <&dmac0 13>; + dma-names = "tx", "rx"; pinctrl-0 = <&uart6m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; @@ -1533,6 +1540,7 @@ uart7: serial@fe6b0000 { clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "tx", "rx"; pinctrl-0 = <&uart7m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; @@ -1547,6 +1555,7 @@ uart8: serial@fe6c0000 { clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 16>, <&dmac0 17>; + dma-names = "tx", "rx"; pinctrl-0 = <&uart8m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; @@ -1561,6 +1570,7 @@ uart9: serial@fe6d0000 { clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 18>, <&dmac0 19>; + dma-names = "tx", "rx"; pinctrl-0 = <&uart9m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; -- 2.56.0