From: Xingui Yang <yangxingui@huawei.com>
To: <mkp@kernel.org>, <jejb@linux.ibm.com>, <john.garry@linux.dev>,
<yanaijie@huawei.com>
Cc: <linux-scsi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linuxarm@huawei.com>, <yangxingui@huawei.com>,
<liuyonglong@huawei.com>, <kangfenglong@huawei.com>
Subject: [PATCH v3 3/4] scsi: hisi_sas: Clear PHY error counts on phyup
Date: Fri, 9 Oct 2026 11:32:37 +0800 [thread overview]
Message-ID: <20261009033238.1076098-4-yangxingui@huawei.com> (raw)
In-Reply-To: <20261009033238.1076098-1-yangxingui@huawei.com>
Some disks generate link errors during link establishment but still
phy up successfully. These intermediate error counts are not cleared
after phyup, leaving stale data for error detection. Clear them on
phyup.
Signed-off-by: Xingui Yang <yangxingui@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 38 +++++++++++++++++---------
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 9c363e237353..030f050731ba 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -280,6 +280,9 @@
#define CHL_INT2_RX_CODE_ERR_OFF 29
#define CHL_INT2_RX_INVLD_DW_OFF 30
#define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
+#define CHL_INT2_RX_ERR_MSK (BIT(CHL_INT2_RX_DISP_ERR_OFF) | \
+ BIT(CHL_INT2_RX_CODE_ERR_OFF) | \
+ BIT(CHL_INT2_RX_INVLD_DW_OFF))
#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
@@ -1061,16 +1064,31 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
}
+static void clear_phy_err_cnt_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK,
+ CHL_INT2_RX_ERR_MSK | irq_msk);
+
+ hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
+ hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
+ hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
+ hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
+ hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, CHL_INT2_RX_ERR_MSK);
+ hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
+}
+
static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
- static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
- BIT(CHL_INT2_RX_CODE_ERR_OFF) |
- BIT(CHL_INT2_RX_INVLD_DW_OFF);
u32 state;
- hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
+ hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK,
+ CHL_INT2_RX_ERR_MSK | irq_msk);
cfg &= ~PHY_CFG_ENA_MSK;
hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
@@ -1085,11 +1103,7 @@ static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
udelay(1);
- hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
- hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
- hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
-
- hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
+ clear_phy_err_cnt_v3_hw(hisi_hba, phy_no);
hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
}
@@ -1671,6 +1685,7 @@ static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
/* Delete timer and set phy_attached atomically */
timer_delete(&phy->timer);
phy->phy_attached = 1;
+ clear_phy_err_cnt_v3_hw(hisi_hba, phy_no);
spin_unlock(&phy->lock);
/*
@@ -1894,9 +1909,6 @@ static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
struct pci_dev *pci_dev = hisi_hba->pci_dev;
struct device *dev = hisi_hba->dev;
- static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
- BIT(CHL_INT2_RX_CODE_ERR_OFF) |
- BIT(CHL_INT2_RX_INVLD_DW_OFF);
irq_value &= ~irq_msk;
if (!irq_value) {
@@ -1920,7 +1932,7 @@ static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
}
- if (pci_dev->revision > 0x20 && (irq_value & msk)) {
+ if (pci_dev->revision > 0x20 && (irq_value & CHL_INT2_RX_ERR_MSK)) {
struct asd_sas_phy *sas_phy = &phy->sas_phy;
struct sas_phy *sphy = sas_phy->phy;
--
2.43.0
next prev parent reply other threads:[~2026-10-09 3:51 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 3:32 [PATCH v3 0/4] scsi: hisi_sas: Some misc fixes Xingui Yang
2026-10-09 3:32 ` [PATCH v3 1/4] scsi: libsas: Fix out-of-bounds memcpy in sas_ssp_task_response() Xingui Yang
2026-10-09 3:32 ` [PATCH v3 2/4] scsi: hisi_sas: Fix incorrect delay values from magic-number cleanup Xingui Yang
2026-10-09 3:32 ` Xingui Yang [this message]
2026-10-09 3:32 ` [PATCH v3 4/4] scsi: hisi_sas: Fix spinup failure for SAS SSP devices in Active_Wait state Xingui Yang
2026-10-09 9:08 ` [PATCH v3 0/4] scsi: hisi_sas: Some misc fixes yangxingui
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