[PATCH 1/4] drm/msm/dpu: keep SSPP priority order for split planes on DPU < 5.0

[Mahadevan P <mahadevan.p@oss.qualcomm.com>]

Before DPU 5.0, the layer mixer places the higher priority SSPP on
the left of a source-split pair. Priority follows the SSPP index
(VIG, RGB, DMA), while allocation prefers DMA, RGB, then VIG.

Swap the two SSPPs when the right one has the lower index. Both are
reserved with the same requirements. Same-SSPP parallel multirect
already puts RECT_0, the higher priority rectangle, on the left.

Fixes: 8c62a31607f6 ("drm/msm/dpu: allow using two SSPP blocks for a single plane")
Assisted-by: LLM
Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 1a471cdf767b..fe43ea9ae864 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1245,6 +1245,10 @@ static int dpu_plane_assign_resource_in_stage(struct dpu_sw_pipe *pipe,
 	r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
 	r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
 
+	if (dpu_kms->catalog->mdss_ver->core_major_ver < 5 &&
+	    r_pipe->sspp->idx < pipe->sspp->idx)
+		swap(pipe->sspp, r_pipe->sspp);
+
 	return 0;
 }
 

-- 
2.34.1