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a=ed25519-sha256; t=1791639504; l=4157; i=mahadevan.p@oss.qualcomm.com; s=20250923; h=from:subject:message-id; bh=rmFIBBdLnwpW2eE/0l3ytGX1iuO0WIb/U+KmegawFdg=; b=R2KZBseePjfVkJAOeHkE5tcvy3+YCr50BkkxV1BOYcfpURVsHwkKo0EmCw80HY9MXspq/aQYn 8awH61Fp+oeCp8uuuiOqev2jmNKrezKsRKehRqqemYL5NjGxezPobyk X-Developer-Key: i=mahadevan.p@oss.qualcomm.com; a=ed25519; pk=wed9wuAek0VbCYfkANx7ujIG4VY0XfCYrffFKPN2p0Y= X-Proofpoint-ORIG-GUID: 4gdvikB8tQYJpVOLALKQsKZbFGLhTAvQ X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEwMDA1NCBTYWx0ZWRfX3VedvnlsJEoA ulsCk/ntgaeC6HIiRDZ1xxeMqRGx6WAPjce8mR95l5T0S95VQGNKzFG9PjUuBvj/V3fKx4Cnm+a CoAuCc2I2Vp4piFBPJkZRNWJJH4OuYw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEwMDA1NCBTYWx0ZWRfX3S2BA6ycp7e1 dXv8v+Ax4ERzPy9xi2jqfcxh9DqlgO4xCwp1MTWhpHiB+IW0yV7mOMs/m7+k09fjcYT4TgMhNnc KgFD4IKen1rvTlJInzcK0jkSXckGPuQ94FW7exNhILwBM56Pz6MbZA6D7YQEc+A+RN38jlROu4L 3ZKO1BE7pJJYSiBQwJItdrXGCezSMoswEex3QH15MwDKcOI3EtcmXkgamIfsJ2CqUaM86L7QbCH joDv6z9mxUF8VdI4NTypjW+T/Le9TJy0wZJ55aP6a71IN+F+ozA2/zowaUp4d/VJLp9A2eqdDq+ UVgAeRObi8IjS96KZAeDivrL/TBegjaL0dsVcGkboca8nsfolAN0EY0P7i0E6WVVFm171KcnAOy 83wtSt7I4ucz7TskAJ2hYd08GIvlFnuLWJpjkgjHKH0udZoN+OS9/6FBiwlIn9XOZi/It7F9V+y nwjg1XhZrD0RpsQAreQ== X-Proofpoint-GUID: 4gdvikB8tQYJpVOLALKQsKZbFGLhTAvQ X-Authority-Analysis: v=2.4 cv=asknmiZV c=1 sm=1 tr=0 ts=6aca3fe0 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=h-rY-VAj1oihTiXfbOoA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-10_02,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 phishscore=0 spamscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610100054 DPU 5.0 introduced SRC_SPLIT_ORDER in bit 4 of SSPP_SRC_OP_MODE and SSPP_SRC_OP_MODE_REC1. For source-split pairs using legacy CTL routing, this field identifies the left source with 0 and the right source with 1. Add a setup_src_split_order() operation for the SSPP register layout used on DPU 5.0 through 12.x. Select SSPP_SRC_OP_MODE for SOLO or RECT0 and SSPP_SRC_OP_MODE_REC1 for RECT1, and update only the ordering bit. Assisted-by: LLM Signed-off-by: Mahadevan P --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 35 +++++++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 11 +++++++++ 2 files changed, 46 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index b5e50fc1916f..f6ec883f9066 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -84,6 +84,7 @@ #define MDSS_MDP_OP_IGC_EN BIT(16) #define MDSS_MDP_OP_FLIP_UD BIT(14) #define MDSS_MDP_OP_FLIP_LR BIT(13) +#define MDSS_MDP_OP_SRC_SPLIT_ORDER BIT(4) #define MDSS_MDP_OP_BWC_EN BIT(0) #define MDSS_MDP_OP_PE_OVERRIDE BIT(31) #define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1) @@ -260,6 +261,38 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, ubwc_ctrl_off, ubwc_error_off); } +void dpu_hw_setup_src_split_order_impl(struct dpu_hw_sspp *ctx, + u32 op_mode_off, bool right) +{ + u32 opmode; + + opmode = DPU_REG_READ(&ctx->hw, op_mode_off); + if (right) + opmode |= MDSS_MDP_OP_SRC_SPLIT_ORDER; + else + opmode &= ~MDSS_MDP_OP_SRC_SPLIT_ORDER; + + DPU_REG_WRITE(&ctx->hw, op_mode_off, opmode); +} + +static void dpu_hw_sspp_setup_src_split_order(struct dpu_sw_pipe *pipe, + bool right) +{ + struct dpu_hw_sspp *ctx = pipe->sspp; + u32 op_mode_off; + + if (!ctx) + return; + + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || + pipe->multirect_index == DPU_SSPP_RECT_0) + op_mode_off = SSPP_SRC_OP_MODE; + else + op_mode_off = SSPP_SRC_OP_MODE_REC1; + + dpu_hw_setup_src_split_order_impl(ctx, op_mode_off, right); +} + void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt, u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off, u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off, @@ -636,6 +669,8 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c, c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress; c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill; c->ops.setup_pe = dpu_hw_sspp_setup_pe_config; + if (mdss_rev->core_major_ver >= 5) + c->ops.setup_src_split_order = dpu_hw_sspp_setup_src_split_order; if (test_bit(DPU_SSPP_QOS, &features)) { c->ops.setup_qos_lut = dpu_hw_sspp_setup_qos_lut; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 69d68cc916b2..9b9ea2e00a00 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -236,6 +236,14 @@ struct dpu_hw_sspp_ops { void (*setup_multirect)(struct dpu_sw_pipe *pipe); + /** + * @setup_src_split_order: program the position of the pipe within + * a source split pair + * @pipe: Pointer to pipe context + * @right: true if the pipe fetches the right half of the pair + */ + void (*setup_src_split_order)(struct dpu_sw_pipe *pipe, bool right); + /** * @setup_sharpening: setup sharpening * @ctx: Pointer to pipe context @@ -349,6 +357,9 @@ void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe, struct dpu_hw_sspp *ctx, u32 op_mode_off); +void dpu_hw_setup_src_split_order_impl(struct dpu_hw_sspp *ctx, + u32 op_mode_off, bool right); + void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt, u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off, u32 unpack_pat_off, u32 format_off, -- 2.34.1