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Sat, 10 Oct 2026 10:59:39 +0000 From: Changhuang Liang To: Stephen Boyd , Brian Masney , Jerome Brunet , Philipp Zabel , Emil Renner Berthing Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Changhuang Liang , Hal Feng Subject: [PATCH v6 2/5] clk: starfive: Add Peripheral-0 domain PLL clock driver Date: Sat, 10 Oct 2026 03:58:56 -0700 Message-Id: <20261010105859.19505-3-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261010105859.19505-1-changhuang.liang@starfivetech.com> References: <20261010105859.19505-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: ZQ0PR01CA0036.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:2::20) To NT0PR01MB1216.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:11::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: NT0PR01MB1216:EE_|NT0PR01MB1005:EE_ X-MS-Office365-Filtering-Correlation-Id: af708082-702b-46ad-01c9-08df26bd947e X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|52116014|7416014|376014|23010399003|22082099003|18002099003|10067099003|261009223027099003|38350700014|56012099006; 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It binds to the per0 system controller node and registers PLL6 using the JHB100 PLL library. Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 12 +++ drivers/clk/starfive/Makefile | 1 + .../starfive/clk-starfive-jhb100-per-pll.c | 76 +++++++++++++++++++ 3 files changed, 89 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per-pll.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 4a7c67445f4c..00c46f5ec976 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -113,6 +113,18 @@ config CLK_STARFIVE_JHB100_PER3 Say yes here to support the peripheral-3 clock controller on the StarFive JHB100 SoC. +config CLK_STARFIVE_JHB100_PER_PLL + bool "StarFive JHB100 peripheral PLL clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + select CLK_STARFIVE_JHB100_PLL + select MFD_SYSCON + default ARCH_STARFIVE + help + Say yes here to support the PLL6 clock generator found in the + peripheral-0 system controller of the StarFive JHB100 SoC. It + provides the parent clock of the peripheral-0 clock + controller. + config CLK_STARFIVE_JHB100_PLL bool diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 3a8f75c55c96..e31ded58bd6f 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) += clk-starfive-jhb100-per2.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PER3) += clk-starfive-jhb100-per3.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_PER_PLL) += clk-starfive-jhb100-per-pll.o obj-$(CONFIG_CLK_STARFIVE_JHB100_PLL) += clk-starfive-jhb100-pll.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0_PLL) += clk-starfive-jhb100-sys0-pll.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-per-pll.c new file mode 100644 index 000000000000..d38116f16935 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-per-pll.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 Peripheral domain PLL Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-starfive-jhb100-pll.h" + +#define JHB100_PLL6_OFFSET 0x00 + +struct jhb100_per_pll_data { + const struct jhb100_pll_info *info; + unsigned int num; +}; + +static const struct jhb100_pll_mult jhb100_pll6_mults[] = { + { .fbdiv = 192, .frac = 0, .refdiv = 1 }, +}; + +static const struct jhb100_pll_info jhb100_per0_pll_info[] = { + JHB100_PLL(JHB100_PER0PLL_PLL6_OUT, "pll6", JHB100_PLL6_OFFSET, + jhb100_pll6_mults, ARRAY_SIZE(jhb100_pll6_mults)), +}; + +static const struct jhb100_per_pll_data jhb100_per0_pll_data = { + .info = jhb100_per0_pll_info, + .num = ARRAY_SIZE(jhb100_per0_pll_info), +}; + +static int jhb100_per_pll_probe(struct platform_device *pdev) +{ + const struct jhb100_per_pll_data *data; + struct device *dev = &pdev->dev; + struct regmap *regmap; + + data = device_get_match_data(dev); + if (!data) + return -ENODEV; + + regmap = syscon_node_to_regmap(dev_of_node(dev)); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "failed to get syscon regmap\n"); + + return devm_jhb100_pll_register(dev, regmap, data->info, data->num); +} + +static const struct of_device_id jhb100_per_pll_match[] = { + { + .compatible = "starfive,jhb100-per0-syscon", + .data = &jhb100_per0_pll_data, + }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_per_pll_driver = { + .probe = jhb100_per_pll_probe, + .driver = { + .name = "clk-starfive-jhb100-per-pll", + .of_match_table = jhb100_per_pll_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(jhb100_per_pll_driver); -- 2.25.1