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Sat, 10 Oct 2026 10:59:40 +0000 From: Changhuang Liang To: Stephen Boyd , Brian Masney , Jerome Brunet , Philipp Zabel , Emil Renner Berthing Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Changhuang Liang , Hal Feng Subject: [PATCH v6 3/5] clk: starfive: Add Peripheral-1 domain PLL clock driver Date: Sat, 10 Oct 2026 03:58:57 -0700 Message-Id: <20261010105859.19505-4-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261010105859.19505-1-changhuang.liang@starfivetech.com> References: <20261010105859.19505-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: ZQ0PR01CA0036.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:2::20) To NT0PR01MB1216.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:11::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: NT0PR01MB1216:EE_|NT0PR01MB1005:EE_ X-MS-Office365-Filtering-Correlation-Id: 9d3d09c8-26f0-43ca-8557-08df26bd9553 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|52116014|7416014|376014|23010399003|22082099003|18002099003|10067099003|261009223027099003|38350700014|56012099006; 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The peripheral PLL driver now also binds to the per1 system controller node and registers PLL7 using the JHB100 PLL library. Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 8 ++++---- .../starfive/clk-starfive-jhb100-per-pll.c | 19 +++++++++++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 00c46f5ec976..1bf64f1b6c58 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -120,10 +120,10 @@ config CLK_STARFIVE_JHB100_PER_PLL select MFD_SYSCON default ARCH_STARFIVE help - Say yes here to support the PLL6 clock generator found in the - peripheral-0 system controller of the StarFive JHB100 SoC. It - provides the parent clock of the peripheral-0 clock - controller. + Say yes here to support the PLL6 and PLL7 clock generators found + in the peripheral-0 and peripheral-1 system controllers of the + StarFive JHB100 SoC. They provide the parent clocks of the + peripheral-0 and peripheral-1 clock controllers. config CLK_STARFIVE_JHB100_PLL bool diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-per-pll.c index d38116f16935..ef01f7d1d5f6 100644 --- a/drivers/clk/starfive/clk-starfive-jhb100-per-pll.c +++ b/drivers/clk/starfive/clk-starfive-jhb100-per-pll.c @@ -19,6 +19,7 @@ #include "clk-starfive-jhb100-pll.h" #define JHB100_PLL6_OFFSET 0x00 +#define JHB100_PLL7_OFFSET 0x40 struct jhb100_per_pll_data { const struct jhb100_pll_info *info; @@ -39,6 +40,20 @@ static const struct jhb100_per_pll_data jhb100_per0_pll_data = { .num = ARRAY_SIZE(jhb100_per0_pll_info), }; +static const struct jhb100_pll_mult jhb100_pll7_mults[] = { + { .fbdiv = 156, .frac = 0, .refdiv = 1 }, +}; + +static const struct jhb100_pll_info jhb100_per1_pll_info[] = { + JHB100_PLL(JHB100_PER1PLL_PLL7_OUT, "pll7", JHB100_PLL7_OFFSET, + jhb100_pll7_mults, ARRAY_SIZE(jhb100_pll7_mults)), +}; + +static const struct jhb100_per_pll_data jhb100_per1_pll_data = { + .info = jhb100_per1_pll_info, + .num = ARRAY_SIZE(jhb100_per1_pll_info), +}; + static int jhb100_per_pll_probe(struct platform_device *pdev) { const struct jhb100_per_pll_data *data; @@ -62,6 +77,10 @@ static const struct of_device_id jhb100_per_pll_match[] = { .compatible = "starfive,jhb100-per0-syscon", .data = &jhb100_per0_pll_data, }, + { + .compatible = "starfive,jhb100-per1-syscon", + .data = &jhb100_per1_pll_data, + }, { /* sentinel */ } }; -- 2.25.1