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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/8] arm64: dts: amlogic: t7: add the ethernet controller Date: Sat, 10 Oct 2026 11:58:58 +0100 Message-ID: <20261010105900.247342-7-tanure@linux.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261010105900.247342-1-tanure@linux.com> References: <20261010105900.247342-1-tanure@linux.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The SoC has a Synopsys gigabit MAC, glue registers for the interface type and clock timing, and a multiplexer that points the management bus at the on-chip 100M PHY or the external pins. None of it was described. The controller reaches memory through a pipeline stage with its own gate that nothing else claims, so it is switched off as unused. The glue registers share a clock with the multiplexer, which probes only after the controller has programmed them: unless the controller holds that clock itself, the writes are lost and the port keeps the bootloader's delays. The on-chip PHY follows the G12A; no board in tree uses it, so it is untested. It stays disabled for boards to enable. Assisted-by: LLM Signed-off-by: Lucas Tanure --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 58 +++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index 7bd53ec16607..94ea22514501 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -250,6 +250,33 @@ gic: interrupt-controller@fff01000 { interrupts = ; }; + ethmac: ethernet@fdc00000 { + compatible = "amlogic,t7-dwmac", + "snps,dwmac-5.10a", + "snps,dwmac"; + reg = <0x0 0xfdc00000 0x0 0x10000>, + <0x0 0xfe024000 0x0 0x8>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&clkc_periphs CLKID_SYS_ETH>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&mpll CLKID_MPLL2>, + <&clkc_periphs CLKID_SYS_AMPIPE_ETH>, + <&clkc_periphs CLKID_SYS_ETHPHY>; + clock-names = "stmmaceth", "clkin0", "clkin1", "pipeline", + "pclk"; + power-domains = <&pwrc PWRC_T7_ETH_ID>; + rx-fifo-depth = <4096>; + tx-fifo-depth = <2048>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + apb4: bus@fe000000 { compatible = "simple-bus"; reg = <0x0 0xfe000000 0x0 0x480000>; @@ -645,6 +672,37 @@ gpio_intc: interrupt-controller@4080 { <10 11 12 13 14 15 16 17 18 19 20 21>; }; + eth_phy: mdio-multiplexer@28000 { + compatible = "amlogic,g12a-mdio-mux"; + reg = <0x0 0x28000 0x0 0xa4>; + clocks = <&clkc_periphs CLKID_SYS_ETHPHY>, + <&xtal>, + <&scmi_clk CLKID_FCLK_50M>; + clock-names = "pclk", "clkin0", "clkin1"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + + ext_mdio: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + int_mdio: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + internal_ephy: ethernet-phy@8 { + compatible = "ethernet-phy-id0180.3301", + "ethernet-phy-ieee802.3-c22"; + interrupts = ; + reg = <8>; + }; + }; + }; + uart_a: serial@78000 { compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart"; reg = <0x0 0x78000 0x0 0x18>; -- 2.56.0