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Sat, 10 Oct 2026 04:56:16 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Chunfeng Yun , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Stephen Boyd , Brian Masney , Jerome Brunet , Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Nicolas Frattaroli , Chen-Yu Tsai , Fabien Parent , chunhui dai , CK Hu , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 7/7] arm64: dts: mediatek: mt8167: Add HDMI display nodes Date: Sat, 10 Oct 2026 13:54:07 +0200 Message-ID: <20261010115539.9237-8-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261010115539.9237-1-l.scorcia@gmail.com> References: <20261010115539.9237-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the required nodes to drive HDMI output on the mt8167 SoC. Signed-off-by: Luca Leonardo Scorcia --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 62 ++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 27cf32d7ae35..ab76e0637eb1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -112,6 +112,27 @@ apmixedsys: apmixedsys@10018000 { #clock-cells = <1>; }; + hdmi_phy: hdmi-phy@10018300 { + compatible = "mediatek,mt8167-hdmi-phy"; + reg = <0 0x10018300 0 0x20>; + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; + clock-names = "pll_ref"; + clock-output-names = "hdmtx_dig_cts"; + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + cec: cec@1001a000 { + compatible = "mediatek,mt8167-cec", "mediatek,mt8173-cec"; + reg = <0 0x1001a000 0 0xbc>; + interrupts = ; + clocks = <&topckgen CLK_TOP_26M_CEC>; + status = "disabled"; + }; + iommu: m4u@10203000 { compatible = "mediatek,mt8167-m4u"; reg = <0 0x10203000 0 0x1000>; @@ -120,6 +141,15 @@ iommu: m4u@10203000 { #iommu-cells = <1>; }; + hdmiddc: i2c@11011000 { + compatible = "mediatek,mt8167-hdmi-ddc", "mediatek,mt8173-hdmi-ddc"; + reg = <0 0x11011000 0 0x10>; + interrupts = ; + clocks = <&topckgen CLK_TOP_26M_HDMI_SIFM>; + clock-names = "ddc-i2c"; + status = "disabled"; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; @@ -145,6 +175,38 @@ smi_common: smi@14017000 { power-domains = <&spm MT8167_POWER_DOMAIN_MM>; }; + hdmi: hdmi@1401b000 { + compatible = "mediatek,mt8167-hdmi"; + reg = <0 0x1401b000 0 0x400>; + clocks = <&mmsys CLK_MM_HDMI_PXL>, + <&mmsys CLK_MM_HDMI_PLL>, + <&mmsys CLK_MM_HDMI_ADSP_BCK>, + <&mmsys CLK_MM_HDMI_SPDIF>; + clock-names = "pixel", "pll", "bclk", "spdif"; + interrupts = ; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + mediatek,syscon-hdmi = <&mmsys 0x900>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + + hdmi0_out: endpoint { }; + }; + }; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt8167-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; -- 2.43.0