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Sat, 10 Oct 2026 06:00:41 -0700 (PDT) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a190c49d5csm162309975e9.3.2026.10.10.06.00.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Oct 2026 06:00:40 -0700 (PDT) From: Navid Ghahremani To: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arnd@arndb.de, linux@armlinux.org.uk, stefandoesinger@gmail.com, robh@kernel.org, krzk@kernel.org, Navid Ghahremani Subject: [PATCH 12/24] dt-bindings: PCI: Add ZTE ZX279128S host controller Date: Sat, 10 Oct 2026 13:59:50 +0100 Message-ID: <20261010130024.177503-13-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261010130024.177503-1-ghahramani.navid@gmail.com> References: <20261010130024.177503-1-ghahramani.navid@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Describe both DesignWare hosts, the two control syscons and the shared Wi-Fi reset lines. The shared-resource model remains an RFC question. Assisted-by: LLM Signed-off-by: Navid Ghahremani --- .../bindings/pci/zte,zx279128s-pcie.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/zte,zx279128s-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/zte,zx279128s-pcie.yaml b/Documentation/devicetree/bindings/pci/zte,zx279128s-pcie.yaml new file mode 100644 index 0000000000..57a4e96610 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/zte,zx279128s-pcie.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/zte,zx279128s-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx279128s PCIe host controller + +maintainers: + - Navid Ghahremani + +description: + The ZTE zx279128s has two PCIe host controllers based on the Synopsys + DesignWare PCIe IP, each with one lane. Their clocks, resets and PHYs are + controlled through the SoC's Top CRM blocks. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: zte,zx279128s-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers + - description: Controller wrapper registers + - description: PCIe configuration space region + + reg-names: + items: + - const: dbi + - const: ctrl + - const: config + + interrupts: + maxItems: 1 + + zte,crm: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: The two Top CRM syscons that hold the clock, reset and PHY + controls of this controller. + items: + - items: + - description: phandle to Top CRM 1 + - items: + - description: phandle to Top CRM 2 + + reset-gpios: + maxItems: 1 + description: Board reset line. A device connected to both controllers + (the MT7915 Wi-Fi chip of the ZTE ZXHN H3600) has its lines listed in + both nodes; the first controller to start resets and releases it. + + enable-gpios: + maxItems: 1 + description: Second board line that is driven together with reset-gpios. + +required: + - reg + - reg-names + - interrupts + - '#interrupt-cells' + - interrupt-map + - interrupt-map-mask + - zte,crm + +unevaluatedProperties: false + +examples: + - | + #include + #include + + pcie@f000000 { + compatible = "zte,zx279128s-pcie"; + reg = <0x0f000000 0x4000>, + <0x09500000 0x1000>, + <0x1c000000 0x200000>; + reg-names = "dbi", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x10000000 0x10000000 0 0x08000000>; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + linux,pci-domain = <0>; + zte,crm = <&topcrm>, <&crm2>; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + }; -- 2.55.0