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Sat, 10 Oct 2026 06:00:42 -0700 (PDT) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a190c49d5csm162309975e9.3.2026.10.10.06.00.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Oct 2026 06:00:42 -0700 (PDT) From: Navid Ghahremani To: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arnd@arndb.de, linux@armlinux.org.uk, stefandoesinger@gmail.com, robh@kernel.org, krzk@kernel.org, Navid Ghahremani Subject: [PATCH 14/24] dt-bindings: net: Add ZTE ZX279128S MDIO controller Date: Sat, 10 Oct 2026 13:59:52 +0100 Message-ID: <20261010130024.177503-15-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261010130024.177503-1-ghahramani.navid@gmail.com> References: <20261010130024.177503-1-ghahramani.navid@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Describe the MDIO register block and its work/register clocks. External- PHY pin selections use pinctrl rather than direct syscon writes. Assisted-by: LLM Signed-off-by: Navid Ghahremani --- .../bindings/net/zte,zx279128s-mdio.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/zte,zx279128s-mdio.yaml diff --git a/Documentation/devicetree/bindings/net/zte,zx279128s-mdio.yaml b/Documentation/devicetree/bindings/net/zte,zx279128s-mdio.yaml new file mode 100644 index 0000000000..49ff7e7b1a --- /dev/null +++ b/Documentation/devicetree/bindings/net/zte,zx279128s-mdio.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/zte,zx279128s-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx279128s MDIO controller + +maintainers: + - Navid Ghahremani + +description: + The MDIO controller of the ZTE zx279128s reaches the PHYs of the integrated + switch and an optional external PHY. On boards with an external PHY, the + default pin state connects the interface to it. + +allOf: + - $ref: mdio.yaml# + +properties: + compatible: + const: zte,zx279128s-mdio + + reg: + maxItems: 1 + + clocks: + items: + - description: work clock, the source of the management clock (MDC) + - description: register (APB) clock + + clock-names: + items: + - const: wclk + - const: pclk + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + mdio@9a101000 { + compatible = "zte,zx279128s-mdio"; + reg = <0x9a101000 0x18>; + clocks = <&lsp1crpm ZX279128S_LSP1_MDIO_WCLK>, + <&lsp1crpm ZX279128S_LSP1_MDIO_PCLK>; + clock-names = "wclk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&ext_phy_pins>; + + ethernet-phy@8 { + reg = <8>; + }; + + ethernet-phy@10 { + reg = <10>; + }; + }; -- 2.55.0