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Sat, 10 Oct 2026 06:00:44 -0700 (PDT) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a190c49d5csm162309975e9.3.2026.10.10.06.00.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Oct 2026 06:00:44 -0700 (PDT) From: Navid Ghahremani To: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arnd@arndb.de, linux@armlinux.org.uk, stefandoesinger@gmail.com, robh@kernel.org, krzk@kernel.org, Navid Ghahremani Subject: [PATCH 16/24] net: phy: Add Sanechips ZX5201 PHY support Date: Sat, 10 Oct 2026 13:59:54 +0100 Message-ID: <20261010130024.177503-17-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261010130024.177503-1-ghahramani.navid@gmail.com> References: <20261010130024.177503-1-ghahramani.navid@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Initialize the external WAN PHY and its SerDes path; generic PHY support handles negotiation. Assisted-by: LLM Signed-off-by: Navid Ghahremani --- drivers/net/phy/Kconfig | 8 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/sanechips.c | 153 ++++++++++++++++++++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 drivers/net/phy/sanechips.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index b4ef927fd4..63620fdfc4 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -416,6 +416,14 @@ config ROCKCHIP_PHY help Currently supports the integrated Ethernet PHY. +config SANECHIPS_PHY + tristate "Sanechips Ethernet PHYs" + help + Currently supports the Sanechips ZX5201 PHY, which the ZTE ZXHN + H3600 uses for its WAN port. The driver sets the PHY up so that + its SerDes interface passes traffic; everything else is handled + by the generic PHY code. + config SMSC_PHY tristate "SMSC PHYs" select CRC16 diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 25c4a3c242..666309f7d0 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -97,6 +97,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o obj-$(CONFIG_REALTEK_PHY) += realtek/ obj-$(CONFIG_RENESAS_PHY) += uPD60620.o obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o +obj-$(CONFIG_SANECHIPS_PHY) += sanechips.o obj-$(CONFIG_SMSC_PHY) += smsc.o obj-$(CONFIG_STE10XP) += ste10Xp.o obj-$(CONFIG_TERANETICS_PHY) += teranetics.o diff --git a/drivers/net/phy/sanechips.c b/drivers/net/phy/sanechips.c new file mode 100644 index 0000000000..bb5129b2bb --- /dev/null +++ b/drivers/net/phy/sanechips.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Sanechips ZX5201 Ethernet PHY + * + * The ZX5201 answers on two MDIO addresses: the copper PHY on its own + * address and its MAC-side SerDes interface on the next one. The copper PHY + * uses the standard registers and the generic PHY code; this driver only adds + * the setup that the PHY needs before it passes traffic. The values come from + * the vendor firmware of the ZTE ZXHN H3600, and most of them are not + * documented. + * + * Copyright (C) 2026 Navid Ghahremani + */ + +#include +#include +#include + +#define PHY_ID_ZX5201 0x84b95011 + +/* Copper PHY vendor registers */ +#define ZX5201_REG18 18 +#define ZX5201_EXT_ADDR 16 /* extended register access: address */ +#define ZX5201_EXT_DATA 17 /* extended register access: data */ +#define ZX5201_REG29 29 + +/* + * SerDes interface registers, at the PHY's MDIO address + 1. The names are + * a best guess from the way the vendor firmware uses them. + */ +#define ZX5201_SDS_WDATA_LO 16 +#define ZX5201_SDS_WDATA_HI 17 +#define ZX5201_SDS_CMD 18 +#define ZX5201_SDS_RDATA_LO 20 +#define ZX5201_SDS_RDATA_HI 21 +#define ZX5201_SDS_REG22 22 +#define ZX5201_SDS_REG27 27 + +static int zx5201_sds_read(struct phy_device *phydev, u32 regnum) +{ + return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr + 1, regnum); +} + +static int zx5201_sds_write(struct phy_device *phydev, u32 regnum, u16 val) +{ + return mdiobus_write(phydev->mdio.bus, phydev->mdio.addr + 1, regnum, + val); +} + +static int zx5201_ext_write(struct phy_device *phydev, u16 reg, u16 val) +{ + int ret; + + ret = phy_write(phydev, ZX5201_EXT_ADDR, reg); + if (ret) + return ret; + + return phy_write(phydev, ZX5201_EXT_DATA, val); +} + +static int zx5201_config_init(struct phy_device *phydev) +{ + static const u16 led_regs[] = { 0xb409, 0xb407, 0xb406, 0xb408 }; + int ret, lo, hi, i; + + ret = phy_write(phydev, ZX5201_REG18, 0x8402); + if (ret) + return ret; + + ret = zx5201_sds_write(phydev, ZX5201_SDS_REG22, 0x0a0f); + if (ret) + return ret; + + ret = zx5201_sds_write(phydev, ZX5201_SDS_REG27, 0x0800); + if (ret) + return ret; + + ret = phy_write(phydev, ZX5201_REG29, 0x0355); + if (ret) + return ret; + + ret = zx5201_ext_write(phydev, 0xb62d, 0x0006); + if (ret) + return ret; + + /* + * This looks like an indirect read-modify-write of SerDes register 4: + * read it, set bits 9-13 of its high half (bits 25-29 of the register) + * to 0b10100, and write it back. + */ + ret = zx5201_sds_write(phydev, ZX5201_SDS_CMD, 0x0004); + if (ret) + return ret; + + hi = zx5201_sds_read(phydev, ZX5201_SDS_RDATA_HI); + if (hi < 0) + return hi; + + lo = zx5201_sds_read(phydev, ZX5201_SDS_RDATA_LO); + if (lo < 0) + return lo; + + ret = zx5201_sds_write(phydev, ZX5201_SDS_WDATA_HI, + (hi & 0xc1ff) | 0x2800); + if (ret) + return ret; + + ret = zx5201_sds_write(phydev, ZX5201_SDS_WDATA_LO, lo); + if (ret) + return ret; + + ret = zx5201_sds_write(phydev, ZX5201_SDS_CMD, 0x0204); + if (ret) + return ret; + + ret = zx5201_sds_read(phydev, ZX5201_SDS_REG22); + if (ret < 0) + return ret; + + ret = zx5201_sds_write(phydev, ZX5201_SDS_REG22, (ret & 0xfff3) | 0x0004); + if (ret) + return ret; + + /* LED control registers, all cleared as the vendor firmware does */ + for (i = 0; i < ARRAY_SIZE(led_regs); i++) { + ret = zx5201_ext_write(phydev, led_regs[i], 0); + if (ret) + return ret; + } + + return 0; +} + +static struct phy_driver sanechips_phy_driver[] = { + { + PHY_ID_MATCH_EXACT(PHY_ID_ZX5201), + .name = "Sanechips ZX5201", + .config_init = zx5201_config_init, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, +}; +module_phy_driver(sanechips_phy_driver); + +static const struct mdio_device_id __maybe_unused sanechips_phy_tbl[] = { + { PHY_ID_MATCH_EXACT(PHY_ID_ZX5201) }, + { } +}; +MODULE_DEVICE_TABLE(mdio, sanechips_phy_tbl); + +MODULE_AUTHOR("Navid Ghahremani "); +MODULE_DESCRIPTION("Sanechips Ethernet PHY driver"); +MODULE_LICENSE("GPL"); -- 2.55.0