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Sat, 10 Oct 2026 06:00:30 -0700 (PDT) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a190c49d5csm162309975e9.3.2026.10.10.06.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Oct 2026 06:00:30 -0700 (PDT) From: Navid Ghahremani To: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arnd@arndb.de, linux@armlinux.org.uk, stefandoesinger@gmail.com, robh@kernel.org, krzk@kernel.org, Navid Ghahremani Subject: [PATCH 01/24] dt-bindings: cache: l2c2x0: Describe ZTE device-read serialization Date: Sat, 10 Oct 2026 13:59:39 +0100 Message-ID: <20261010130024.177503-2-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261010130024.177503-1-ghahramani.navid@gmail.com> References: <20261010130024.177503-1-ghahramani.navid@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Describe the observed interconnect deadlock workaround separately from the ARM implementation. This property and API remain an RFC requiring ARM and DT review. Assisted-by: LLM Signed-off-by: Navid Ghahremani --- Documentation/devicetree/bindings/cache/l2c2x0.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/cache/l2c2x0.yaml b/Documentation/devicetree/bindings/cache/l2c2x0.yaml index ee604117ff..0295846cde 100644 --- a/Documentation/devicetree/bindings/cache/l2c2x0.yaml +++ b/Documentation/devicetree/bindings/cache/l2c2x0.yaml @@ -176,6 +176,15 @@ properties: description: enable ECC protection on the L2 cache type: boolean + zte,l2c-io-read-lock: + description: On the ZTE zx279128s, a CPU read from a PCIe device that is + still outstanding when an L2C-310 range or sync operation starts hangs + the interconnect. This property makes the L2C-310 maintenance operations + take a lock that the drivers of such devices also take around their + register reads. Valid only when the arm,pl310-cache compatible string + is used. + type: boolean + arm,outer-sync-disable: description: disable the outer sync operation on the L2 cache. Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that -- 2.55.0