From: Anisa Su <anisa.su887@gmail.com>
To: linux-cxl@vger.kernel.org
Cc: nvdimm@lists.linux.dev, linux-kernel@vger.kernel.org,
Dave Jiang <dave.jiang@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <iweiny@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
Fan Ni <nifan.cxl@gmail.com>, Li Ming <ming.li@zohomail.com>,
Benjamin Cheatham <benjamin.cheatham@amd.com>,
Gregory Price <gourry@gourry.net>,
Richard Cheng <icheng@nvidia.com>,
Anisa Su <anisa.su@samsung.com>
Subject: [PATCH v16 0/8] DCD Prep Series
Date: Sun, 11 Oct 2026 07:54:51 +0900 [thread overview]
Message-ID: <20261010225852.10727-1-anisa.su@samsung.com> (raw)
These are the first eight patches of the Dynamic Capacity Device (DCD)
series. They set up: DCD enumeration, CDAT handling for DC partitions,
the event interrupt plumbing, a preparatory refactor, and
documentation of the DPA partition layout. They stand alone and keep DCD
disabled. They are not dependent on the rest of the series.
Patch 1 detects the 48h command set and then leaves mds->dcd_supported
false. The flag is only turned on by the series that adds DCD event
handling, so every DCD specific path added here is shut off at runtime:
cxl_configure_dcd() never runs, no DC partition is created, no DCD
interrupt is armed, and the CXL_PARTMODE_DYNAMIC_RAM paths are
unreachable. The intent is to land the enumeration and plumbing while
the extent to DAX pipeline is still under review.
Based on v7.3-rc6
v15: https://lore.kernel.org/linux-cxl/20261007201828.952-1-anisa.su@samsung.com/
v15 -> v16 Changes:
===================
A quick respin:
- Patch 2: cxl_configure_dcd() took Identify Total Capacity as the end
of static capacity, but Total Capacity is only required to be >=
ram + pmem. The static end now comes from the last static partition's end dpa
+1 instead of info->size. Check that DC starts from there. (Richard).
- Patch 3: dsmas_entry.qos_class initialized as CXL_QOS_CLASS_INVALID, so a
DSMAS entry that is skipped for lack of DSLBIS, or whose QTG lookup
fails, no longer reaches update_perf_entry() with qos_class 0, which
is a valid class. (Sashiko).
The DSMAD handle check now checks handle > U8_MAX instead of
handle & ~0xFF (Dave).
- Patch 6: when the DCD vector cannot be requested, tell the device
not to use the vector: dcd_settings is cleared with
Set Event Interrupt Policy, so a device does not keep signalling a
vector with no handler while the
host considers DCD off. The Set command is re-factored into a new helper
cxl_event_set_int_policy() (Richard).
All other patches are unchanged.
I kept the review tags on patch 3, since the changes are minimal and
dropped tags from 2 and 6.
Patch organization
==================
1-3: enumerate DCD command support, read the DC configuration, and pick
up DSMAS data for DC partitions.
4-6: split event msgnum configuration from irq setup, factor out the
interrupt policy check, then configure the DCD event interrupt.
7: preparatory refactor -- enforce partition order while collapsing
the ram/pmem specific partition helpers into one.
8: document the DPA partition layout the previous patches enforce,
and where Linux is stricter than the specification.
Testing
=======
This series leaves mds->dcd_supported false on purpose, so
cxl_configure_dcd(), cxl_dev_dc_identify() and cxl_dc_check() are
unreachable at runtime as posted. The tests below are done with the rest
of the series on top, otherwise testing would not yield any meaningful
results.
HW:
Tested add and release of one 2G tagged extent on a DCD with a sharable
partition, driven from the system's BMC with FM-API Initiate Dynamic
Capacity Add / Release over MCTP, to confirm the DCD interrupt
configuration and the DSMAS attributes are read properly. The device
is sharable, so an add without a tag and sequence number is refused.
cxl_test:
ndctl cxl test suite
16 of 17 pass, cxl-features.sh skips for lack of FWCTL
Anisa Su (1):
Documentation/cxl: Document DPA partition layout and ordering rules
Ira Weiny (7):
cxl/mbox: Flag support for Dynamic Capacity Devices (DCD)
cxl/mem: Read dynamic capacity configuration from the device
cxl/cdat: Gather DSMAS data for DCD partitions
cxl/events: Split event msgnum configuration from irq setup
cxl/pci: Factor out interrupt policy check
cxl/mem: Configure dynamic capacity interrupts
cxl/core: Enforce partition order/simplify partition calls
.../driver-api/cxl/linux/cxl-driver.rst | 35 +++
Documentation/driver-api/cxl/maturity-map.rst | 4 +
drivers/cxl/core/cdat.c | 99 +++++-
drivers/cxl/core/hdm.c | 24 +-
drivers/cxl/core/mbox.c | 285 ++++++++++++++++++
drivers/cxl/core/memdev.c | 100 ++++--
drivers/cxl/cxl.h | 14 +-
drivers/cxl/cxlmem.h | 88 +++++-
drivers/cxl/mem.c | 2 +-
drivers/cxl/pci.c | 207 ++++++++++---
include/cxl/cxl.h | 29 +-
tools/testing/cxl/test/mem.c | 2 +-
12 files changed, 792 insertions(+), 97 deletions(-)
base-commit: a90ee4305c4a5df72c11b31dacfdc76e00fcf78a
--
2.43.0
next reply other threads:[~2026-10-10 22:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-10 22:54 Anisa Su [this message]
2026-10-10 22:54 ` [PATCH v16 1/8] cxl/mbox: Flag support for Dynamic Capacity Devices (DCD) Anisa Su
2026-10-10 22:54 ` [PATCH v16 2/8] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
2026-10-10 22:54 ` [PATCH v16 3/8] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
2026-10-10 22:54 ` [PATCH v16 4/8] cxl/events: Split event msgnum configuration from irq setup Anisa Su
2026-10-10 22:54 ` [PATCH v16 5/8] cxl/pci: Factor out interrupt policy check Anisa Su
2026-10-10 22:54 ` [PATCH v16 6/8] cxl/mem: Configure dynamic capacity interrupts Anisa Su
2026-10-10 22:54 ` [PATCH v16 7/8] cxl/core: Enforce partition order/simplify partition calls Anisa Su
2026-10-10 22:54 ` [PATCH v16 8/8] Documentation/cxl: Document DPA partition layout and ordering rules Anisa Su
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