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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0dPzloicBc0m56JLD6myvdwtm2AqM9g6qTomVt+ZAeQdN9cRgL4QXhv4YJD27QUFC3IHTpFtVDi6UtZbqxbclGLHlARGYVFipHy3Xo6rUCNFZh4FywMJepBClxyhLd5uMjMDwHjuybLtluHZGAnILmMBwPRDDrJsvNSnLz7JDe4gzWGMkaQVWJ/9Pk6d5/Zc7Dnh/4BTT15NsnyzpQD0GBgjdYzsA+NdslBAyouxdKEHkLweUsOmiZ1Z/z6WvK63mDFJQ6DJKHevNaGbLTli1TFYTgmQbwjUIVdrRIfCiM/RyOmg2YL0BLrCQLgXHrC1V37alFCelrOTb7eH0kPRHyY8vjGw0HCK6LlwsyAOTgLb9p4nH6yXBuD4pS02qJu8Ld+EI8pG6EBufJhDuFd09O+NowZzOn+uMqYi3ai1dFIYO/FPY02wp7LpD4E/AFc/ X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2026 17:40:14.7948 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73ec4c75-3611-4eee-90b7-08df27beb559 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: MA3PEPF00000405.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI0PR08MB11018 The perfcnt_size register, needed to size the FW-side ring buffer, is comprised out of two fields, FIRMWARE_SIZE and HARDWARE_SIZE, indicating the size of the corresponding components of a single sample. The total size of a single sample in that ring buffer is the sum of the two. The perfcnt_config register configures the size of the ring buffer, the counter set requested by the user, and whether the optional metadata block is required. For newer FW revisions, the perfcnt_features register reports the presence of an optional metadata block. GPUs with arch major 11 or greater also report the number of performance counters in a single counter block via the GPU_PRFCNT_FEATURES. Signed-off-by: Lukas Zapolskas --- drivers/gpu/drm/panthor/panthor_fw.h | 9 ++++++++- drivers/gpu/drm/panthor/panthor_gpu_regs.h | 4 ++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panthor/panthor_fw.h b/drivers/gpu/drm/panthor/panthor_fw.h index a99a9b6f4825..124e2b40b15f 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.h +++ b/drivers/gpu/drm/panthor/panthor_fw.h @@ -198,8 +198,12 @@ struct panthor_fw_global_control_iface { u32 output_va; u32 group_num; u32 group_stride; +#define GLB_PERFCNT_FW_SIZE(x) ((((x) >> 16) << 8)) +#define GLB_PERFCNT_HW_SIZE(x) (((x) & GENMASK(15, 0)) << 8) u32 perfcnt_size; u32 instr_features; +#define PERFCNT_FEATURES_MD_SIZE(x) (((x) & GENMASK(3, 0)) << 8) + u32 perfcnt_features; }; struct panthor_fw_global_input_iface { @@ -208,7 +212,7 @@ struct panthor_fw_global_input_iface { #define GLB_CFG_ALLOC_EN BIT(2) #define GLB_CFG_POWEROFF_TIMER BIT(3) #define GLB_PROTM_ENTER BIT(4) -#define GLB_PERFCNT_EN BIT(5) +#define GLB_PERFCNT_ENABLE BIT(5) #define GLB_PERFCNT_SAMPLE BIT(6) #define GLB_COUNTER_EN BIT(7) #define GLB_PING BIT(8) @@ -248,6 +252,9 @@ struct panthor_fw_global_input_iface { u64 perfcnt_base; u32 perfcnt_extract; u32 reserved3[3]; +#define GLB_PERFCNT_CONFIG_SIZE(x) ((x) & GENMASK(7, 0)) +#define GLB_PERFCNT_CONFIG_SET(x) (((x) & GENMASK(1, 0)) << 8) +#define GLB_PERFCNT_METADATA_ENABLE BIT(10) u32 perfcnt_config; u32 perfcnt_csg_select; u32 perfcnt_fw_enable; diff --git a/drivers/gpu/drm/panthor/panthor_gpu_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_regs.h index 4c5b953796e4..2f0877068e44 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu_regs.h +++ b/drivers/gpu/drm/panthor/panthor_gpu_regs.h @@ -23,6 +23,7 @@ #define GPU_TILER_FEATURES 0xC #define GPU_MEM_FEATURES 0x10 #define GROUPS_L2_COHERENT BIT(0) +#define GPU_MEM_FEATURES_L2_SLICES(x) ((((x) & GENMASK(11, 8)) >> 8) + 1) #define GPU_MMU_FEATURES 0x14 #define GPU_MMU_FEATURES_VA_BITS(x) ((x) & GENMASK(7, 0)) @@ -69,6 +70,9 @@ #define GPU_FEATURES_RAY_INTERSECTION BIT(2) #define GPU_FEATURES_RAY_TRAVERSAL BIT(5) +#define GPU_PRFCNT_FEATURES 0x68 +#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE(x) (((x) & GENMASK(7, 0)) << 8) + #define GPU_TIMESTAMP_OFFSET 0x88 #define GPU_CYCLE_COUNT 0x90 #define GPU_TIMESTAMP 0x98 -- 2.43.0