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From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <jic23@kernel.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>,
	linux-tegra@vger.kernel.org,
	Srirangan Madhavan <smadhavan@nvidia.com>
Subject: [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks
Date: Sun, 11 Oct 2026 02:14:22 +0000	[thread overview]
Message-ID: <20261011021422.3428136-17-smadhavan@nvidia.com> (raw)
In-Reply-To: <20261011021422.3428136-1-smadhavan@nvidia.com>

Test cxl_hdm_unpack_decoder() when cxl_test loads, failing module loading
if a check fails. Cover range boundaries and overflow, an all-ones base,
zero-size and uncommitted decoders, and a locked host-only decoder with
12-way interleave. Verify the decoded fields for valid inputs.

Run the checks separately from the watermark hooks, using a helper
exported only by mock cxl_core. No PCI device or MMIO is needed.

Cache refresh, retained-state comparison, and reset restoration need
follow-up tests with additional mock support. These checks do not cover
reset sequencing or hardware cache invalidation.

Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
---
 tools/testing/cxl/cxl_core_test.c | 78 +++++++++++++++++++++++++++++++
 tools/testing/cxl/cxl_core_test.h |  8 ++++
 tools/testing/cxl/test/cxl.c      |  5 ++
 3 files changed, 91 insertions(+)
 create mode 100644 tools/testing/cxl/cxl_core_test.h

diff --git a/tools/testing/cxl/cxl_core_test.c b/tools/testing/cxl/cxl_core_test.c
index 464a9255e4d6..8072146643bd 100644
--- a/tools/testing/cxl/cxl_core_test.c
+++ b/tools/testing/cxl/cxl_core_test.c
@@ -1,6 +1,84 @@
 // SPDX-License-Identifier: GPL-2.0
 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */
 
+#include <linux/bitfield.h>
+#include <linux/sizes.h>
+#include "cxl.h"
+#include "core.h"
+#include "cxl_core_test.h"
 #include "watermark.h"
 
 cxl_test_watermark(cxl_core);
+
+/* Exercise the shared unpacker without HDM MMIO or a PCI device. */
+int cxl_test_hdm_ranges(void)
+{
+	static const struct {
+		const char *name;
+		u32 ctrl;
+		u64 base;
+		u64 size;
+		int rc;
+		unsigned long flags;
+		int ways;
+		int granularity;
+		enum cxl_decoder_type target_type;
+	} cases[] = {
+		{ "valid", CXL_HDM_DECODER0_CTRL_COMMITTED,
+		  SZ_1G, SZ_256M, 0, CXL_DECODER_F_ENABLE,
+		  1, 256, CXL_DECODER_DEVMEM },
+		{ "overflow", CXL_HDM_DECODER0_CTRL_COMMITTED,
+		  U64_MAX - 127, 256, -ENXIO },
+		{ "all-ones base", CXL_HDM_DECODER0_CTRL_COMMITTED,
+		  U64_MAX, SZ_256M, -ENXIO },
+		{ "last address", CXL_HDM_DECODER0_CTRL_COMMITTED,
+		  U64_MAX - 255, 256, 0, CXL_DECODER_F_ENABLE,
+		  1, 256, CXL_DECODER_DEVMEM },
+		{ "zero size", CXL_HDM_DECODER0_CTRL_COMMITTED,
+		  SZ_1G, 0, 0, CXL_DECODER_F_ENABLE,
+		  1, 256, CXL_DECODER_DEVMEM },
+		{ "uncommitted stale size", 0,
+		  SZ_1G, SZ_256M, 0, 0, 1, 256, 0 },
+		{ "locked host-only interleave",
+		  CXL_HDM_DECODER0_CTRL_COMMITTED | CXL_HDM_DECODER0_CTRL_LOCK |
+		  CXL_HDM_DECODER0_CTRL_HOSTONLY |
+		  FIELD_PREP_CONST(CXL_HDM_DECODER0_CTRL_IW_MASK, 10) |
+		  FIELD_PREP_CONST(CXL_HDM_DECODER0_CTRL_IG_MASK, 2),
+		  SZ_1G, SZ_256M, 0, CXL_DECODER_F_ENABLE | CXL_DECODER_F_LOCK,
+		  12, SZ_1K, CXL_DECODER_HOSTONLYMEM },
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(cases); i++) {
+		struct cxl_decoder_config config;
+		u64 size;
+		int rc;
+
+		rc = cxl_hdm_unpack_decoder(&config, 3, cases[i].ctrl,
+					    cases[i].base, cases[i].size);
+		if (rc != cases[i].rc) {
+			pr_err("cxl_test: HDM %s returned %d, expected %d\n",
+			       cases[i].name, rc, cases[i].rc);
+			return -EINVAL;
+		}
+		if (rc)
+			continue;
+		size = cases[i].size;
+		if (!(cases[i].flags & CXL_DECODER_F_ENABLE))
+			size = 0;
+		if (config.id != 3 || config.hpa_range.start != cases[i].base ||
+		    range_len(&config.hpa_range) != size ||
+		    config.flags != cases[i].flags ||
+		    config.interleave_ways != cases[i].ways ||
+		    config.interleave_granularity != cases[i].granularity ||
+		    config.target_type != cases[i].target_type) {
+			pr_err("cxl_test: HDM %s decoded unexpected state\n",
+			       cases[i].name);
+			return -EINVAL;
+		}
+	}
+
+	pr_info("cxl_test: HDM decoder range tests passed\n");
+	return 0;
+}
+
+EXPORT_SYMBOL_GPL(cxl_test_hdm_ranges);
diff --git a/tools/testing/cxl/cxl_core_test.h b/tools/testing/cxl/cxl_core_test.h
new file mode 100644
index 000000000000..48392759cd22
--- /dev/null
+++ b/tools/testing/cxl/cxl_core_test.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2026 NVIDIA Corporation & Affiliates */
+#ifndef _CXL_CORE_TEST_H_
+#define _CXL_CORE_TEST_H_
+
+int cxl_test_hdm_ranges(void);
+
+#endif /* _CXL_CORE_TEST_H_ */
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index 034d3a923b2c..5e6e9a8a21d9 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -12,6 +12,7 @@
 #include <cxlmem.h>
 
 #include "../watermark.h"
+#include "../cxl_core_test.h"
 #include "mock.h"
 
 static int interleave_arithmetic;
@@ -2453,6 +2454,10 @@ static __init int cxl_test_init(void)
 	cxl_pmem_test();
 	cxl_port_test();
 
+	rc = cxl_test_hdm_ranges();
+	if (rc)
+		return rc;
+
 	register_cxl_mock_ops(&cxl_mock_ops);
 
 	cxl_mock_pool = gen_pool_create(ilog2(SZ_2M), NUMA_NO_NODE);
-- 
2.43.0


      parent reply	other threads:[~2026-10-11  2:15 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-11  2:14 [PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 05/16] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 06/16] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 08/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 12/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 13/16] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 14/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-11  2:14 ` [PATCH v15 15/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-11  2:14 ` Srirangan Madhavan [this message]

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