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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-169a1becf08sm29748733c88.5.2026.10.12.00.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2026 00:23:43 -0700 (PDT) From: Varadarajan Narayanan Date: Mon, 12 Oct 2026 12:53:09 +0530 Subject: [PATCH v7 09/11] arm64: dts: qcom: ipq5210: Add I2C nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261012-08-dts-v7-9-77bd3d68d850@oss.qualcomm.com> References: <20261012-08-dts-v7-0-77bd3d68d850@oss.qualcomm.com> In-Reply-To: <20261012-08-dts-v7-0-77bd3d68d850@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEyMDAyOSBTYWx0ZWRfX4aKkax556lSV DlQtb/EbuvKOzIAWHyOW1yqC/aQXPgq6w9Ri75mUMu4bZWVFk+vPYdgaLePTR6xIgZIEPQTksUp Jr/rHc7wgtHYTC3k1wWuyIRKyIBnsV8= X-Proofpoint-GUID: S68Vm31DFmKxJxqZejLRayDfjEIF4LPk X-Proofpoint-ORIG-GUID: S68Vm31DFmKxJxqZejLRayDfjEIF4LPk X-Authority-Analysis: v=2.4 cv=ePGGH3p1 c=1 sm=1 tr=0 ts=6acc8b02 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=GftUwNuSPIKaBOPN2qUA:9 a=QEXdDO2ut3YA:10 a=vBUdepa8ALXHeOFLBtFW:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEyMDAyOSBTYWx0ZWRfXycXGIM+NGa8L Qnow0h3iJoxeOSsG8Y5n8jfb4A/Zfdylz7rCQVzWcMKrLh3iSv7b3r34ncle6yiE755UceCpvRy EoTSMcreaZv7zgyNXJ4pmpPrG7OPHNif7GeW4/BmL+/UVyFJLZm16f/EojKnCxwa6MLPip57SZ2 wNlPbjLvnIMDYliTQyBIFA7zTMt1/okCrCEAo7RQF/P+bOHVEyL2r/4x4jxwRQZbmHv2z5VcJRw QS5vEvXdkCxqbLgruBzv0v+vcloO9vrgzjsn52/VjgD9GEazVhb6CjpEFze+wvmBkvDSP248x65 1i7aBJ/bmcGzlaOBn3F6A/kbgpYfH3uEJzI3TV9FFpuooe8RCVwNCCkdERbAEn/IvjQJJWa9jvo ZFdIyuNRLBtrWjGEYRFmKzO1DR81XLvEPHCvnt/4h2022FVCnWeKEM9yhX3jogN1AH4GP9GLChW iK2DFuHkLmgv9LL8mtA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-12_02,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 malwarescore=0 adultscore=0 bulkscore=0 phishscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610120029 Add the QUPv3 I2C controller nodes for IPQ5210 and enable I2C0 with the required pin configuration on RDP504. Signed-off-by: Varadarajan Narayanan --- .../arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 23 ++++++++++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 42 ++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi index 0f7a8f2d886b..0fd85b78e5b7 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi @@ -59,6 +59,13 @@ vreg_misc_0p925: regulator-usb-0p925 { }; }; +&i2c0 { + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + &pcie0 { pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -197,6 +204,22 @@ clock-pins { }; }; + qup_i2c0_default: qup-i2c0-default-state { + qup-i2c0-scl-pins { + pins = "gpio20"; + function = "qup_se2"; + drive-strength = <6>; + bias-pull-up; + }; + + qup-i2c0-sda-pins { + pins = "gpio21"; + function = "qup_se2"; + drive-strength = <6>; + bias-pull-up; + }; + }; + qup_uart1_default_state: qup-uart1-default-state { pins = "gpio38", "gpio39"; function = "qup_se1"; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 22ab99ca0903..fdfeedcf5618 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -427,6 +427,48 @@ uart1: serial@1a84000 { status = "disabled"; }; + + i2c0: i2c@1a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE2_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = ; + assigned-clocks = <&gcc GCC_QUPV3_WRAP_SE2_CLK>; + assigned-clock-rates = <32000000>; + status = "disabled"; + }; + + i2c1: i2c@1a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE3_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = ; + assigned-clocks = <&gcc GCC_QUPV3_WRAP_SE3_CLK>; + assigned-clock-rates = <32000000>; + status = "disabled"; + }; + + i2c2: i2c@1a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE5_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = ; + assigned-clocks = <&gcc GCC_QUPV3_WRAP_SE5_CLK>; + assigned-clock-rates = <32000000>; + status = "disabled"; + }; }; sdhc: mmc@7804000 { -- 2.34.1