From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E3E335C6AA; Mon, 12 Oct 2026 17:32:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791826378; cv=none; b=ma6hpzf57zQP55uf1j0VLEYg8lBiEEEH4pVoHBR+i/PmGa8JMkBbcNoD5ppydALS7vUad3BPri16WQhBnqPF5tmlmKoTN2CdGo7XafPWfF4pmY2jFV90KamU+91Y/Gxss1lShXl+XK+/OHmXQ494dbM4FY0Vm+k3YY7qzL0fW8Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791826378; c=relaxed/simple; bh=Zzzint5ECeIvn557DthDmutEppVqwPr3W2qzFUq9hXQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Fr9UOGYjOjVbZk8BSOTyu0DNssE7bi0r07vkejytm218sltH3MvgEwqVZQ4ie4Oawy5l2+WcQbtBfnmZ4+wWyv5N9E/V2Pdtfb+iEJPLVo9uueiBWPfUuPRYHRQ+5Syiu5V5JsNRsLQI7R7C+h4jaKhtQySoCT9+BPhe9FcU4pw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YPQcRPHM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YPQcRPHM" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1AFD1C2BCFB; Mon, 12 Oct 2026 17:32:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1791826378; bh=Zzzint5ECeIvn557DthDmutEppVqwPr3W2qzFUq9hXQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YPQcRPHMiHFpvaPYGgkrdMBZTa95ZZvUJkCelMbYhi0ppjX7g59fzGEKaHn8gjLXT qJr1ehexZU5WkNl0ew9KmHVNkREqnuz2+XUQSU9mKCcExPJGRsGC/Vu25BdDrRM7rT VGJv1pTS2pe/CbniYxDMYaBPyGXOe6O2fliSpQTCy6DI1T05tk+8O0DGojOCd7g9rq jxte83/3LC4EuZrCpYeAHA2bChzumdLVrafGP7R7wvJ/vrQ6s1WQDANFjRXaJ5Q0fO FHjLEoSZOCYaoJAU29gfkwfStVe27ZsVY5olQAILSX3wAeTwbHREacoBmXOlh2WmPz 03Pd9HNWbbeXw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF49ECA9EDE; Mon, 12 Oct 2026 17:32:57 +0000 (UTC) From: Fil Dunsky via B4 Relay Date: Mon, 12 Oct 2026 20:32:56 +0300 Subject: [PATCH 01/11] dt-bindings: interrupt-controller: Add Cortina Systems CS7542 peripheral interrupt controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261012-b4-cs75xx-s2-v1-1-8a7641b7b79c@gmail.com> References: <20261012-b4-cs75xx-s2-v1-0-8a7641b7b79c@gmail.com> In-Reply-To: <20261012-b4-cs75xx-s2-v1-0-8a7641b7b79c@gmail.com> To: Thomas Gleixner , Radu Rendec , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Andi Shyti , Wim Van Sebroeck , Guenter Roeck , Russell King , Arnd Bergmann , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org, linux-watchdog@vger.kernel.org, Fil Dunsky X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791826375; l=2339; i=filipp.dunsky@gmail.com; s=20260930; h=from:subject:message-id; bh=A+5dV3NaQB/TuZqJfC9IFKI7zbkGEtJkk6VbEFbSsyk=; b=aS7EyPYv896uSAFVSpeoN2KGEke+u9sKmCFiUaXmk3QSkRG6Bj2JkJpRbyXEwmVEax2tFvalI as0O/tKQFgdCq5Oms7G/wa9kkkM1FEZ/zREBL8A3vtQyeS7uNmEA5wL X-Developer-Key: i=filipp.dunsky@gmail.com; a=ed25519; pk=JAYP8e2rJ54DHOmhNtXud8rl1igAaAXoOHxtJmVXI1g= X-Endpoint-Received: by B4 Relay for filipp.dunsky@gmail.com/20260930 with auth_id=1085 X-Original-From: Fil Dunsky Reply-To: filipp.dunsky@gmail.com From: Fil Dunsky The low speed peripherals of the Cortina Systems CS75xx SoCs share one GIC interrupt. A small controller in the peripheral register block reports which of its 15 sources are asserted and allows masking them. Signed-off-by: Fil Dunsky --- .../interrupt-controller/cortina,cs7542-intc.yaml | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/cortina,cs7542-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/cortina,cs7542-intc.yaml new file mode 100644 index 000000000..2963acaf7 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/cortina,cs7542-intc.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/cortina,cs7542-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cortina Systems CS7542 peripheral interrupt controller + +maintainers: + - Fil Dunsky + +description: + The low speed peripherals of the Cortina Systems CS75xx (Goldengate G2) + SoCs (two software interrupts, two timers, the AXI bridge, SPI, the five + GPIO banks, I2C, MDIO, SSP and the random number generator) share one GIC + interrupt. This controller has a status register showing the level of the + 15 sources and an enable register to mask them. The sources are cleared in + the peripherals themselves. + +properties: + compatible: + const: cortina,cs7542-intc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + description: + The number of the source, 0 to 14. All sources are active high level + interrupts. + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include + + interrupt-controller@f0070004 { + compatible = "cortina,cs7542-intc"; + reg = <0xf0070004 0x8>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; -- 2.53.0